2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 * 2019 David Shah <dave@ds0.me>
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 * Tech-mapping rules for decomposing arbitrarily-sized $mul cells
23 * into an equivalent collection of smaller `DSP_NAME cells (with the
24 * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
25 * to $shl and $add cells.
29 `ifndef DSP_A_MAXWIDTH
30 $fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
32 `ifndef DSP_B_MAXWIDTH
33 $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
35 `ifndef DSP_B_MAXWIDTH
36 $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
38 `ifndef DSP_A_MAXWIDTH_PARTIAL
39 `define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
41 `ifndef DSP_B_MAXWIDTH_PARTIAL
42 `define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
46 $fatal(1, "Macro DSP_NAME must be defined");
49 `define MAX(a,b) (a > b ? a : b)
50 `define MIN(a,b) (a < b ? a : b)
52 (* techmap_celltype = "$mul $__mul" *)
53 module _80_mul (A, B, Y);
54 parameter A_SIGNED = 0;
55 parameter B_SIGNED = 0;
56 parameter A_WIDTH = 1;
57 parameter B_WIDTH = 1;
58 parameter Y_WIDTH = 1;
60 input [A_WIDTH-1:0] A;
61 input [B_WIDTH-1:0] B;
62 output [Y_WIDTH-1:0] Y;
64 parameter _TECHMAP_CELLTYPE_ = "";
69 else if (A_WIDTH < `DSP_A_MINWIDTH)
70 wire _TECHMAP_FAIL_ = 1;
73 else if (B_WIDTH < `DSP_B_MINWIDTH)
74 wire _TECHMAP_FAIL_ = 1;
77 else if (Y_WIDTH < `DSP_Y_MINWIDTH)
78 wire _TECHMAP_FAIL_ = 1;
81 else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
85 .A_WIDTH(A_WIDTH + 1),
86 .B_WIDTH(B_WIDTH + 1),
94 else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
101 ) _TECHMAP_REPLACE_ (
107 wire [1023:0] _TECHMAP_DO_ = "proc; clean";
109 `ifdef DSP_SIGNEDONLY
110 localparam sign_headroom = 1;
112 localparam sign_headroom = 0;
116 if (A_WIDTH > `DSP_A_MAXWIDTH) begin
117 localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
118 localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
119 localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
120 localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
121 if (A_SIGNED && B_SIGNED) begin
122 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
123 wire signed [last_Y_WIDTH-1:0] last_partial;
124 wire signed [Y_WIDTH-1:0] partial_sum [n:0];
127 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
128 wire [last_Y_WIDTH-1:0] last_partial;
129 wire [Y_WIDTH-1:0] partial_sum [n:0];
132 for (i = 0; i < n; i=i+1) begin:sliceA
134 .A_SIGNED(sign_headroom),
136 .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
138 .Y_WIDTH(partial_Y_WIDTH)
140 .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
144 // TODO: Currently a 'cascade' approach to summing the partial
145 // products is taken here, but a more efficient 'binary
146 // reduction' approach also exists...
148 assign partial_sum[i] = partial[i];
150 // Rewrite the following statement explicitly in order
151 // to save on a call to 'opt_expr -fine' which would
152 // optimise away the '<<' op and trim size of adder
153 //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
154 if (A_SIGNED && B_SIGNED)
155 assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]);
157 assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)];
158 assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
165 .A_WIDTH(last_A_WIDTH),
167 .Y_WIDTH(last_Y_WIDTH)
169 .A(A[A_WIDTH-1 -: last_A_WIDTH]),
173 //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
174 if (A_SIGNED && B_SIGNED)
175 assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]);
177 assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)];
178 assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
179 assign Y = partial_sum[n];
181 else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
182 localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
183 localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
184 localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
185 localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
186 if (A_SIGNED && B_SIGNED) begin
187 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
188 wire signed [last_Y_WIDTH-1:0] last_partial;
189 wire signed [Y_WIDTH-1:0] partial_sum [n:0];
192 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
193 wire [last_Y_WIDTH-1:0] last_partial;
194 wire [Y_WIDTH-1:0] partial_sum [n:0];
197 for (i = 0; i < n; i=i+1) begin:sliceB
200 .B_SIGNED(sign_headroom),
202 .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
203 .Y_WIDTH(partial_Y_WIDTH)
206 .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
209 // TODO: Currently a 'cascade' approach to summing the partial
210 // products is taken here, but a more efficient 'binary
211 // reduction' approach also exists...
213 assign partial_sum[i] = partial[i];
215 // Rewrite the following statement explicitly in order
216 // to save on a call to 'opt_expr -fine' which would
217 // optimise away the '<<' op and trim size of adder
218 //assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
219 if (A_SIGNED && B_SIGNED)
220 assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
222 assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
223 assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
231 .B_WIDTH(last_B_WIDTH),
232 .Y_WIDTH(last_Y_WIDTH)
235 .B(B[B_WIDTH-1 -: last_B_WIDTH]),
238 //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
239 if (A_SIGNED && B_SIGNED)
240 assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
242 assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
243 assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
244 assign Y = partial_sum[n];
248 wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
250 wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
252 wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
254 wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
259 .A_WIDTH(`DSP_A_MAXWIDTH),
260 .B_WIDTH(`DSP_B_MAXWIDTH),
261 .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
262 ) _TECHMAP_REPLACE_ (
272 (* techmap_celltype = "$mul $__mul" *)
273 module _90_soft_mul (A, B, Y);
274 parameter A_SIGNED = 0;
275 parameter B_SIGNED = 0;
276 parameter A_WIDTH = 1;
277 parameter B_WIDTH = 1;
278 parameter Y_WIDTH = 1;
280 input [A_WIDTH-1:0] A;
281 input [B_WIDTH-1:0] B;
282 output [Y_WIDTH-1:0] Y;
284 // Indirection necessary since mapping
285 // back to $mul will cause recursion
287 if (A_SIGNED && !B_SIGNED)
294 ) _TECHMAP_REPLACE_ (
299 else if (!A_SIGNED && B_SIGNED)
306 ) _TECHMAP_REPLACE_ (
318 ) _TECHMAP_REPLACE_ (