techlibs/common/mul2dsp.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *                2019  David Shah    <dave@ds0.me>
   7  *
   8  *  Permission to use, copy, modify, and/or distribute this software for any
   9  *  purpose with or without fee is hereby granted, provided that the above
  10  *  copyright notice and this permission notice appear in all copies.
  11  *
  12  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  *  ---
  21  *
  22  *  Tech-mapping rules for decomposing arbitrarily-sized $mul cells
  23  *  into an equivalent collection of smaller `DSP_NAME cells (with the
  24  *  same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
  25  *  to $shl and $add cells.
  26  *
  27  */
  28
  29 `ifndef DSP_A_MAXWIDTH
  30 $fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
  31 `endif
  32 `ifndef DSP_B_MAXWIDTH
  33 $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
  34 `endif
  35 `ifndef DSP_B_MAXWIDTH
  36 $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
  37 `endif
  38 `ifndef DSP_A_MAXWIDTH_PARTIAL
  39 `define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
  40 `endif
  41 `ifndef DSP_B_MAXWIDTH_PARTIAL
  42 `define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
  43 `endif
  44
  45 `ifndef DSP_NAME
  46 $fatal(1, "Macro DSP_NAME must be defined");
  47 `endif
  48
  49 `define MAX(a,b) (a > b ? a : b)
  50 `define MIN(a,b) (a < b ? a : b)
  51
  52 (* techmap_celltype = "$mul $__mul" *)
  53 module _80_mul (A, B, Y);
  54         parameter A_SIGNED = 0;
  55         parameter B_SIGNED = 0;
  56         parameter A_WIDTH = 1;
  57         parameter B_WIDTH = 1;
  58         parameter Y_WIDTH = 1;
  59
  60         input [A_WIDTH-1:0] A;
  61         input [B_WIDTH-1:0] B;
  62         output [Y_WIDTH-1:0] Y;
  63
  64         parameter _TECHMAP_CELLTYPE_ = "";
  65
  66         generate
  67         if (0) begin end
  68 `ifdef DSP_A_MINWIDTH
  69         else if (A_WIDTH < `DSP_A_MINWIDTH)
  70                 wire _TECHMAP_FAIL_ = 1;
  71 `endif
  72 `ifdef DSP_B_MINWIDTH
  73         else if (B_WIDTH < `DSP_B_MINWIDTH)
  74                 wire _TECHMAP_FAIL_ = 1;
  75 `endif
  76 `ifdef DSP_Y_MINWIDTH
  77         else if (Y_WIDTH < `DSP_Y_MINWIDTH)
  78                 wire _TECHMAP_FAIL_ = 1;
  79 `endif
  80         else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
  81                 wire _TECHMAP_FAIL_ = 1;
  82 `ifdef DSP_SIGNEDONLY
  83         else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
  84                 \$mul #(
  85                         .A_SIGNED(1),
  86                         .B_SIGNED(1),
  87                         .A_WIDTH(A_WIDTH + 1),
  88                         .B_WIDTH(B_WIDTH + 1),
  89                         .Y_WIDTH(Y_WIDTH)
  90                 ) _TECHMAP_REPLACE_ (
  91                         .A({1'b0, A}),
  92                         .B({1'b0, B}),
  93                         .Y(Y)
  94                 );
  95 `endif
  96         else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
  97                 \$mul #(
  98                         .A_SIGNED(B_SIGNED),
  99                         .B_SIGNED(A_SIGNED),
 100                         .A_WIDTH(B_WIDTH),
 101                         .B_WIDTH(A_WIDTH),
 102                         .Y_WIDTH(Y_WIDTH)
 103                 ) _TECHMAP_REPLACE_ (
 104                         .A(B),
 105                         .B(A),
 106                         .Y(Y)
 107                 );
 108         else begin
 109                 wire [1023:0] _TECHMAP_DO_ = "proc; clean";
 110
 111 `ifdef DSP_SIGNEDONLY
 112                 localparam sign_headroom = 1;
 113 `else
 114                 localparam sign_headroom = 0;
 115 `endif
 116
 117                 genvar i;
 118                 if (A_WIDTH > `DSP_A_MAXWIDTH) begin
 119                         localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
 120                         localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
 121                         localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
 122                         localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
 123                         if (A_SIGNED && B_SIGNED) begin
 124                                 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
 125                                 wire signed [last_Y_WIDTH-1:0] last_partial;
 126                                 wire signed [Y_WIDTH-1:0] partial_sum [n:0];
 127                         end
 128                         else begin
 129                                 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
 130                                 wire [last_Y_WIDTH-1:0] last_partial;
 131                                 wire [Y_WIDTH-1:0] partial_sum [n:0];
 132                         end
 133
 134                         for (i = 0; i < n; i=i+1) begin:slice
 135                                 \$__mul #(
 136                                         .A_SIGNED(sign_headroom),
 137                                         .B_SIGNED(B_SIGNED),
 138                                         .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
 139                                         .B_WIDTH(B_WIDTH),
 140                                         .Y_WIDTH(partial_Y_WIDTH)
 141                                 ) mul_slice (
 142                                         .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
 143                                         .B(B),
 144                                         .Y(partial[i])
 145                                 );
 146                                 // TODO: Currently a 'cascade' approach to summing the partial
 147                                 //       products is taken here, but a more efficient 'binary
 148                                 //       reduction' approach also exists...
 149                                 if (i == 0)
 150                                         assign partial_sum[i] = partial[i];
 151                                 else
 152                                         assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
 153                         end
 154
 155                         \$__mul #(
 156                                 .A_SIGNED(A_SIGNED),
 157                                 .B_SIGNED(B_SIGNED),
 158                                 .A_WIDTH(last_A_WIDTH),
 159                                 .B_WIDTH(B_WIDTH),
 160                                 .Y_WIDTH(last_Y_WIDTH)
 161                         ) mul_slice_last (
 162                                 .A(A[A_WIDTH-1 -: last_A_WIDTH]),
 163                                 .B(B),
 164                                 .Y(last_partial)
 165                         );
 166                         assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
 167                         assign Y = partial_sum[n];
 168                 end
 169                 else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
 170                         localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
 171                         localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
 172                         localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
 173                         localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
 174                         if (A_SIGNED && B_SIGNED) begin
 175                                 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
 176                                 wire signed [last_Y_WIDTH-1:0] last_partial;
 177                                 wire signed [Y_WIDTH-1:0] partial_sum [n:0];
 178                         end
 179                         else begin
 180                                 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
 181                                 wire [last_Y_WIDTH-1:0] last_partial;
 182                                 wire [Y_WIDTH-1:0] partial_sum [n:0];
 183                         end
 184
 185                         for (i = 0; i < n; i=i+1) begin:slice
 186                                 \$__mul #(
 187                                         .A_SIGNED(A_SIGNED),
 188                                         .B_SIGNED(sign_headroom),
 189                                         .A_WIDTH(A_WIDTH),
 190                                         .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
 191                                         .Y_WIDTH(partial_Y_WIDTH)
 192                                 ) mul (
 193                                         .A(A),
 194                                         .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
 195                                         .Y(partial[i])
 196                                 );
 197                                 // TODO: Currently a 'cascade' approach to summing the partial
 198                                 //       products is taken here, but a more efficient 'binary
 199                                 //       reduction' approach also exists...
 200                                 if (i == 0)
 201                                         assign partial_sum[i] = partial[i];
 202                                 else
 203                                         assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
 204                         end
 205
 206                         \$__mul #(
 207                                 .A_SIGNED(A_SIGNED),
 208                                 .B_SIGNED(B_SIGNED),
 209                                 .A_WIDTH(A_WIDTH),
 210                                 .B_WIDTH(last_B_WIDTH),
 211                                 .Y_WIDTH(last_Y_WIDTH)
 212                         ) mul_last (
 213                                 .A(A),
 214                                 .B(B[B_WIDTH-1 -: last_B_WIDTH]),
 215                                 .Y(last_partial)
 216                         );
 217                         assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
 218                         assign Y = partial_sum[n];
 219                 end
 220                 else begin
 221                         if (A_SIGNED)
 222                                 wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
 223                         else
 224                                 wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
 225                         if (B_SIGNED)
 226                                 wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
 227                         else
 228                                 wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
 229
 230                         `DSP_NAME #(
 231                                 .A_SIGNED(A_SIGNED),
 232                                 .B_SIGNED(B_SIGNED),
 233                                 .A_WIDTH(`DSP_A_MAXWIDTH),
 234                                 .B_WIDTH(`DSP_B_MAXWIDTH),
 235                                 .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
 236                         ) _TECHMAP_REPLACE_ (
 237                                 .A(Aext),
 238                                 .B(Bext),
 239                                 .Y(Y)
 240                         );
 241                 end
 242         end
 243         endgenerate
 244 endmodule
 245
 246 (* techmap_celltype = "$mul $__mul" *)
 247 module _90_soft_mul (A, B, Y);
 248         parameter A_SIGNED = 0;
 249         parameter B_SIGNED = 0;
 250         parameter A_WIDTH = 1;
 251         parameter B_WIDTH = 1;
 252         parameter Y_WIDTH = 1;
 253
 254         input [A_WIDTH-1:0] A;
 255         input [B_WIDTH-1:0] B;
 256         output [Y_WIDTH-1:0] Y;
 257
 258         // Indirection necessary since mapping
 259         //   back to $mul will cause recursion
 260         generate
 261         if (A_SIGNED && !B_SIGNED)
 262                 \$__soft_mul #(
 263                         .A_SIGNED(A_SIGNED),
 264                         .B_SIGNED(1),
 265                         .A_WIDTH(A_WIDTH),
 266                         .B_WIDTH(B_WIDTH+1),
 267                         .Y_WIDTH(Y_WIDTH)
 268                 ) _TECHMAP_REPLACE_ (
 269                         .A(A),
 270                         .B({1'b0,B}),
 271                         .Y(Y)
 272                 );
 273         else if (!A_SIGNED && B_SIGNED)
 274                 \$__soft_mul #(
 275                         .A_SIGNED(1),
 276                         .B_SIGNED(B_SIGNED),
 277                         .A_WIDTH(A_WIDTH+1),
 278                         .B_WIDTH(B_WIDTH),
 279                         .Y_WIDTH(Y_WIDTH)
 280                 ) _TECHMAP_REPLACE_ (
 281                         .A({1'b0,A}),
 282                         .B(B),
 283                         .Y(Y)
 284                 );
 285         else
 286                 \$__soft_mul #(
 287                         .A_SIGNED(A_SIGNED),
 288                         .B_SIGNED(B_SIGNED),
 289                         .A_WIDTH(A_WIDTH),
 290                         .B_WIDTH(B_WIDTH),
 291                         .Y_WIDTH(Y_WIDTH)
 292                 ) _TECHMAP_REPLACE_ (
 293                         .A(A),
 294                         .B(B),
 295                         .Y(Y)
 296                 );
 297         endgenerate
 298 endmodule