techlibs/common/mul2dsp.v

   1 // From Eddie Hung
   2 // extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220
   3 // revised by Andre DeHon
   4 // further revised by David Shah
   5 `ifndef DSP_A_MAXWIDTH
   6 $error("Macro DSP_A_MAXWIDTH must be defined");
   7 `endif
   8 `ifndef DSP_B_MAXWIDTH
   9 $error("Macro DSP_B_MAXWIDTH must be defined");
  10 `endif
  11
  12 `ifndef DSP_NAME
  13 $error("Macro DSP_NAME must be defined");
  14 `endif
  15
  16 `define MAX(a,b) (a > b ? a : b)
  17 `define MIN(a,b) (a < b ? a : b)
  18
  19 module \$mul (A, B, Y);
  20         parameter A_SIGNED = 0;
  21         parameter B_SIGNED = 0;
  22         parameter A_WIDTH = 1;
  23         parameter B_WIDTH = 1;
  24         parameter Y_WIDTH = 1;
  25
  26         input [A_WIDTH-1:0] A;
  27         input [B_WIDTH-1:0] B;
  28         output [Y_WIDTH-1:0] Y;
  29
  30         generate
  31         if (A_SIGNED != B_SIGNED)
  32                 wire _TECHMAP_FAIL_ = 1;
  33 `ifdef DSP_SIGNEDONLY
  34         else if (!A_SIGNED) begin
  35                 wire [1:0] dummy;
  36                 \$mul #(
  37                         .A_SIGNED(1),
  38                         .B_SIGNED(1),
  39                         .A_WIDTH(A_WIDTH + 1),
  40                         .B_WIDTH(B_WIDTH + 1),
  41                         .Y_WIDTH(Y_WIDTH + 2)
  42                 ) _TECHMAP_REPLACE_ (
  43                         .A({1'b0, A}),
  44                         .B({1'b0, B}),
  45                         .Y({dummy, Y})
  46                 );
  47         end
  48 `endif
  49         // NB: A_SIGNED == B_SIGNED == 0 from here
  50         else if (A_WIDTH >= B_WIDTH)
  51                 \$__mul_gen #(
  52                         .A_SIGNED(A_SIGNED),
  53                         .B_SIGNED(B_SIGNED),
  54                         .A_WIDTH(A_WIDTH),
  55                         .B_WIDTH(B_WIDTH),
  56                         .Y_WIDTH(Y_WIDTH)
  57                 ) _TECHMAP_REPLACE_ (
  58                         .A(A),
  59                         .B(B),
  60                         .Y(Y)
  61                 );
  62         else
  63                 \$__mul_gen #(
  64                         .A_SIGNED(B_SIGNED),
  65                         .B_SIGNED(A_SIGNED),
  66                         .A_WIDTH(B_WIDTH),
  67                         .B_WIDTH(A_WIDTH),
  68                         .Y_WIDTH(Y_WIDTH)
  69                 ) _TECHMAP_REPLACE_ (
  70                         .A(B),
  71                         .B(A),
  72                         .Y(Y)
  73                 );
  74         endgenerate
  75 endmodule
  76
  77 module \$__mul_gen (A, B, Y);
  78         parameter A_SIGNED = 0;
  79         parameter B_SIGNED = 0;
  80         parameter A_WIDTH = 1;
  81         parameter B_WIDTH = 1;
  82         parameter Y_WIDTH = 1;
  83
  84         input [A_WIDTH-1:0] A;
  85         input [B_WIDTH-1:0] B;
  86         output [Y_WIDTH-1:0] Y;
  87
  88         wire [1023:0] _TECHMAP_DO_ = "proc; clean";
  89
  90 `ifdef DSP_SIGNEDONLY
  91         localparam sign_headroom = 1;
  92 `else
  93         localparam sign_headroom = 0;
  94 `endif
  95
  96         genvar i;
  97         generate
  98                 if (A_WIDTH > `DSP_A_MAXWIDTH) begin
  99                         localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);
 100                         localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
 101                         if (A_SIGNED && B_SIGNED) begin
 102                                 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
 103                                 wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
 104                         end
 105                         else begin
 106                                 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
 107                                 wire [Y_WIDTH-1:0] partial_sum [n-1:0];
 108                         end
 109
 110                         \$__mul_gen #(
 111                                 .A_SIGNED(sign_headroom),
 112                                 .B_SIGNED(B_SIGNED),
 113                                 .A_WIDTH(`DSP_A_MAXWIDTH),
 114                                 .B_WIDTH(B_WIDTH),
 115                                 .Y_WIDTH(partial_Y_WIDTH)
 116                         ) mul_slice_first (
 117                                 .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}),
 118                                 .B(B),
 119                                 .Y(partial[0])
 120                         );
 121                         assign partial_sum[0] = partial[0];
 122
 123                         for (i = 1; i < n-1; i=i+1) begin:slice
 124                                 \$__mul_gen #(
 125                                         .A_SIGNED(sign_headroom),
 126                                         .B_SIGNED(B_SIGNED),
 127                                         .A_WIDTH(`DSP_A_MAXWIDTH),
 128                                         .B_WIDTH(B_WIDTH),
 129                                         .Y_WIDTH(partial_Y_WIDTH)
 130                                 ) mul_slice (
 131                                         .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}),
 132                                         .B(B),
 133                                         .Y(partial[i])
 134                                 );
 135                                 assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
 136                         end
 137
 138                         \$__mul_gen #(
 139                                 .A_SIGNED(A_SIGNED),
 140                                 .B_SIGNED(B_SIGNED),
 141                                 .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)),
 142                                 .B_WIDTH(B_WIDTH),
 143                                 .Y_WIDTH(partial_Y_WIDTH)
 144                         ) mul_slice_last (
 145                                 .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]),
 146                                 .B(B),
 147                                 .Y(partial[n-1])
 148                         );
 149                         assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
 150                         assign Y = partial_sum[n-1];
 151                 end
 152                 else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
 153                         localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom);
 154                         localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);
 155                         if (A_SIGNED && B_SIGNED) begin
 156                                 wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
 157                                 wire signed [Y_WIDTH-1:0] partial_sum [n-1:0];
 158                         end
 159                         else begin
 160                                 wire [partial_Y_WIDTH-1:0] partial [n-1:0];
 161                                 wire [Y_WIDTH-1:0] partial_sum [n-1:0];
 162                         end
 163
 164                         \$__mul_gen #(
 165                                 .A_SIGNED(A_SIGNED),
 166                                 .B_SIGNED(sign_headroom),
 167                                 .A_WIDTH(A_WIDTH),
 168                                 .B_WIDTH(`DSP_B_MAXWIDTH),
 169                                 .Y_WIDTH(partial_Y_WIDTH)
 170                         ) mul_first (
 171                                 .A(A),
 172                                 .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}),
 173                                 .Y(partial[0])
 174                         );
 175                         assign partial_sum[0] = partial[0];
 176
 177                         for (i = 1; i < n-1; i=i+1) begin:slice
 178                                 \$__mul_gen #(
 179                                         .A_SIGNED(A_SIGNED),
 180                                         .B_SIGNED(sign_headroom),
 181                                         .A_WIDTH(A_WIDTH),
 182                                         .B_WIDTH(`DSP_B_MAXWIDTH),
 183                                         .Y_WIDTH(partial_Y_WIDTH)
 184                                 ) mul (
 185                                         .A(A),
 186                                         .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}),
 187                                         .Y(partial[i])
 188                                 );
 189                                 assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1];
 190                         end
 191
 192                         \$__mul_gen #(
 193                                 .A_SIGNED(A_SIGNED),
 194                                 .B_SIGNED(B_SIGNED),
 195                                 .A_WIDTH(A_WIDTH),
 196                                 .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)),
 197                                 .Y_WIDTH(partial_Y_WIDTH)
 198                         ) mul_last (
 199                                 .A(A),
 200                                 .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
 201                                 .Y(partial[n-1])
 202                         );
 203                         assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
 204                         assign Y = partial_sum[n-1];
 205                 end
 206                 else begin
 207                         if (A_SIGNED)
 208                                 wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
 209                         else
 210                                 wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
 211                         if (B_SIGNED)
 212                                 wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
 213                         else
 214                                 wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
 215
 216                         `DSP_NAME #(
 217                                 .A_SIGNED(A_SIGNED),
 218                                 .B_SIGNED(B_SIGNED),
 219                                 .A_WIDTH(`DSP_A_MAXWIDTH),
 220                                 .B_WIDTH(`DSP_B_MAXWIDTH),
 221                                 .Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH),
 222                         ) _TECHMAP_REPLACE_ (
 223                                 .A(Aext),
 224                                 .B(Bext),
 225                                 .Y(Y)
 226                         );
 227                 end
 228         endgenerate
 229 endmodule
 230
 231