techlibs/common/simlib.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Simulation Library.
  21  *
  22  *  This Verilog library contains simple simulation models for the internal
  23  *  cells ($not, ...) generated by the frontends and used in most passes.
  24  *
  25  *  This library can be used to verify the internal netlists as generated
  26  *  by the different frontends and passes.
  27  *
  28  *  Note that memory can only be simulated when all $memrd and $memwr cells
  29  *  have been merged to stand-alone $mem cells (this is what the "memory_collect"
  30  *  pass is doing).
  31  *
  32  */
  33
  34 // --------------------------------------------------------
  35
  36 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  37 //-
  38 //-     $not (A, Y)
  39 //-
  40 //- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.
  41 //-
  42 module \$not (A, Y);
  43
  44 parameter A_SIGNED = 0;
  45 parameter A_WIDTH = 0;
  46 parameter Y_WIDTH = 0;
  47
  48 input [A_WIDTH-1:0] A;
  49 output [Y_WIDTH-1:0] Y;
  50
  51 generate
  52         if (A_SIGNED) begin:BLOCK1
  53                 assign Y = ~$signed(A);
  54         end else begin:BLOCK2
  55                 assign Y = ~A;
  56         end
  57 endgenerate
  58
  59 endmodule
  60
  61
  62 // --------------------------------------------------------
  63
  64 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  65 //-
  66 //-     $pos (A, Y)
  67 //-
  68 //- A buffer. This corresponds to the Verilog unary prefix '+' operator.
  69 //-
  70 module \$pos (A, Y);
  71
  72 parameter A_SIGNED = 0;
  73 parameter A_WIDTH = 0;
  74 parameter Y_WIDTH = 0;
  75
  76 input [A_WIDTH-1:0] A;
  77 output [Y_WIDTH-1:0] Y;
  78
  79 generate
  80         if (A_SIGNED) begin:BLOCK1
  81                 assign Y = $signed(A);
  82         end else begin:BLOCK2
  83                 assign Y = A;
  84         end
  85 endgenerate
  86
  87 endmodule
  88
  89 // --------------------------------------------------------
  90
  91 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  92 //-
  93 //-     $neg (A, Y)
  94 //-
  95 //- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.
  96 //-
  97 module \$neg (A, Y);
  98
  99 parameter A_SIGNED = 0;
 100 parameter A_WIDTH = 0;
 101 parameter Y_WIDTH = 0;
 102
 103 input [A_WIDTH-1:0] A;
 104 output [Y_WIDTH-1:0] Y;
 105
 106 generate
 107         if (A_SIGNED) begin:BLOCK1
 108                 assign Y = -$signed(A);
 109         end else begin:BLOCK2
 110                 assign Y = -A;
 111         end
 112 endgenerate
 113
 114 endmodule
 115
 116 // --------------------------------------------------------
 117
 118 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 119 //-
 120 //-     $and (A, B, Y)
 121 //-
 122 //- A bit-wise AND. This corresponds to the Verilog '&' operator.
 123 //-
 124 module \$and (A, B, Y);
 125
 126 parameter A_SIGNED = 0;
 127 parameter B_SIGNED = 0;
 128 parameter A_WIDTH = 0;
 129 parameter B_WIDTH = 0;
 130 parameter Y_WIDTH = 0;
 131
 132 input [A_WIDTH-1:0] A;
 133 input [B_WIDTH-1:0] B;
 134 output [Y_WIDTH-1:0] Y;
 135
 136 generate
 137         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 138                 assign Y = $signed(A) & $signed(B);
 139         end else begin:BLOCK2
 140                 assign Y = A & B;
 141         end
 142 endgenerate
 143
 144 endmodule
 145
 146 // --------------------------------------------------------
 147
 148 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 149 //-
 150 //-     $or (A, B, Y)
 151 //-
 152 //- A bit-wise OR. This corresponds to the Verilog '|' operator.
 153 //-
 154 module \$or (A, B, Y);
 155
 156 parameter A_SIGNED = 0;
 157 parameter B_SIGNED = 0;
 158 parameter A_WIDTH = 0;
 159 parameter B_WIDTH = 0;
 160 parameter Y_WIDTH = 0;
 161
 162 input [A_WIDTH-1:0] A;
 163 input [B_WIDTH-1:0] B;
 164 output [Y_WIDTH-1:0] Y;
 165
 166 generate
 167         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 168                 assign Y = $signed(A) | $signed(B);
 169         end else begin:BLOCK2
 170                 assign Y = A | B;
 171         end
 172 endgenerate
 173
 174 endmodule
 175
 176 // --------------------------------------------------------
 177
 178 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 179 //-
 180 //-     $xor (A, B, Y)
 181 //-
 182 //- A bit-wise XOR. This corresponds to the Verilog '^' operator.
 183 //-
 184 module \$xor (A, B, Y);
 185
 186 parameter A_SIGNED = 0;
 187 parameter B_SIGNED = 0;
 188 parameter A_WIDTH = 0;
 189 parameter B_WIDTH = 0;
 190 parameter Y_WIDTH = 0;
 191
 192 input [A_WIDTH-1:0] A;
 193 input [B_WIDTH-1:0] B;
 194 output [Y_WIDTH-1:0] Y;
 195
 196 generate
 197         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 198                 assign Y = $signed(A) ^ $signed(B);
 199         end else begin:BLOCK2
 200                 assign Y = A ^ B;
 201         end
 202 endgenerate
 203
 204 endmodule
 205
 206 // --------------------------------------------------------
 207
 208 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 209 //-
 210 //-     $xnor (A, B, Y)
 211 //-
 212 //- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.
 213 //-
 214 module \$xnor (A, B, Y);
 215
 216 parameter A_SIGNED = 0;
 217 parameter B_SIGNED = 0;
 218 parameter A_WIDTH = 0;
 219 parameter B_WIDTH = 0;
 220 parameter Y_WIDTH = 0;
 221
 222 input [A_WIDTH-1:0] A;
 223 input [B_WIDTH-1:0] B;
 224 output [Y_WIDTH-1:0] Y;
 225
 226 generate
 227         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 228                 assign Y = $signed(A) ~^ $signed(B);
 229         end else begin:BLOCK2
 230                 assign Y = A ~^ B;
 231         end
 232 endgenerate
 233
 234 endmodule
 235
 236 // --------------------------------------------------------
 237
 238 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 239 //-
 240 //-     $reduce_and (A, B, Y)
 241 //-
 242 //- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.
 243 //-
 244 module \$reduce_and (A, Y);
 245
 246 parameter A_SIGNED = 0;
 247 parameter A_WIDTH = 0;
 248 parameter Y_WIDTH = 0;
 249
 250 input [A_WIDTH-1:0] A;
 251 output [Y_WIDTH-1:0] Y;
 252
 253 generate
 254         if (A_SIGNED) begin:BLOCK1
 255                 assign Y = &$signed(A);
 256         end else begin:BLOCK2
 257                 assign Y = &A;
 258         end
 259 endgenerate
 260
 261 endmodule
 262
 263 // --------------------------------------------------------
 264
 265 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 266 //-
 267 //-     $reduce_or (A, B, Y)
 268 //-
 269 //- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.
 270 //-
 271 module \$reduce_or (A, Y);
 272
 273 parameter A_SIGNED = 0;
 274 parameter A_WIDTH = 0;
 275 parameter Y_WIDTH = 0;
 276
 277 input [A_WIDTH-1:0] A;
 278 output [Y_WIDTH-1:0] Y;
 279
 280 generate
 281         if (A_SIGNED) begin:BLOCK1
 282                 assign Y = |$signed(A);
 283         end else begin:BLOCK2
 284                 assign Y = |A;
 285         end
 286 endgenerate
 287
 288 endmodule
 289
 290 // --------------------------------------------------------
 291
 292 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 293 //-
 294 //-     $reduce_xor (A, B, Y)
 295 //-
 296 //- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.
 297 //-
 298 module \$reduce_xor (A, Y);
 299
 300 parameter A_SIGNED = 0;
 301 parameter A_WIDTH = 0;
 302 parameter Y_WIDTH = 0;
 303
 304 input [A_WIDTH-1:0] A;
 305 output [Y_WIDTH-1:0] Y;
 306
 307 generate
 308         if (A_SIGNED) begin:BLOCK1
 309                 assign Y = ^$signed(A);
 310         end else begin:BLOCK2
 311                 assign Y = ^A;
 312         end
 313 endgenerate
 314
 315 endmodule
 316
 317 // --------------------------------------------------------
 318
 319 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 320 //-
 321 //-     $reduce_xnor (A, B, Y)
 322 //-
 323 //- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.
 324 //-
 325 module \$reduce_xnor (A, Y);
 326
 327 parameter A_SIGNED = 0;
 328 parameter A_WIDTH = 0;
 329 parameter Y_WIDTH = 0;
 330
 331 input [A_WIDTH-1:0] A;
 332 output [Y_WIDTH-1:0] Y;
 333
 334 generate
 335         if (A_SIGNED) begin:BLOCK1
 336                 assign Y = ~^$signed(A);
 337         end else begin:BLOCK2
 338                 assign Y = ~^A;
 339         end
 340 endgenerate
 341
 342 endmodule
 343
 344 // --------------------------------------------------------
 345
 346 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 347 //-
 348 //-     $reduce_bool (A, B, Y)
 349 //-
 350 //- An OR reduction. This cell type is used instead of $reduce_or when a signal is
 351 //- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.
 352 //-
 353 module \$reduce_bool (A, Y);
 354
 355 parameter A_SIGNED = 0;
 356 parameter A_WIDTH = 0;
 357 parameter Y_WIDTH = 0;
 358
 359 input [A_WIDTH-1:0] A;
 360 output [Y_WIDTH-1:0] Y;
 361
 362 generate
 363         if (A_SIGNED) begin:BLOCK1
 364                 assign Y = !(!$signed(A));
 365         end else begin:BLOCK2
 366                 assign Y = !(!A);
 367         end
 368 endgenerate
 369
 370 endmodule
 371
 372 // --------------------------------------------------------
 373
 374 module \$shl (A, B, Y);
 375
 376 parameter A_SIGNED = 0;
 377 parameter B_SIGNED = 0;
 378 parameter A_WIDTH = 0;
 379 parameter B_WIDTH = 0;
 380 parameter Y_WIDTH = 0;
 381
 382 input [A_WIDTH-1:0] A;
 383 input [B_WIDTH-1:0] B;
 384 output [Y_WIDTH-1:0] Y;
 385
 386 generate
 387         if (A_SIGNED) begin:BLOCK1
 388                 assign Y = $signed(A) << B;
 389         end else begin:BLOCK2
 390                 assign Y = A << B;
 391         end
 392 endgenerate
 393
 394 endmodule
 395
 396 // --------------------------------------------------------
 397
 398 module \$shr (A, B, Y);
 399
 400 parameter A_SIGNED = 0;
 401 parameter B_SIGNED = 0;
 402 parameter A_WIDTH = 0;
 403 parameter B_WIDTH = 0;
 404 parameter Y_WIDTH = 0;
 405
 406 input [A_WIDTH-1:0] A;
 407 input [B_WIDTH-1:0] B;
 408 output [Y_WIDTH-1:0] Y;
 409
 410 generate
 411         if (A_SIGNED) begin:BLOCK1
 412                 assign Y = $signed(A) >> B;
 413         end else begin:BLOCK2
 414                 assign Y = A >> B;
 415         end
 416 endgenerate
 417
 418 endmodule
 419
 420 // --------------------------------------------------------
 421
 422 module \$sshl (A, B, Y);
 423
 424 parameter A_SIGNED = 0;
 425 parameter B_SIGNED = 0;
 426 parameter A_WIDTH = 0;
 427 parameter B_WIDTH = 0;
 428 parameter Y_WIDTH = 0;
 429
 430 input [A_WIDTH-1:0] A;
 431 input [B_WIDTH-1:0] B;
 432 output [Y_WIDTH-1:0] Y;
 433
 434 generate
 435         if (A_SIGNED) begin:BLOCK1
 436                 assign Y = $signed(A) <<< B;
 437         end else begin:BLOCK2
 438                 assign Y = A <<< B;
 439         end
 440 endgenerate
 441
 442 endmodule
 443
 444 // --------------------------------------------------------
 445
 446 module \$sshr (A, B, Y);
 447
 448 parameter A_SIGNED = 0;
 449 parameter B_SIGNED = 0;
 450 parameter A_WIDTH = 0;
 451 parameter B_WIDTH = 0;
 452 parameter Y_WIDTH = 0;
 453
 454 input [A_WIDTH-1:0] A;
 455 input [B_WIDTH-1:0] B;
 456 output [Y_WIDTH-1:0] Y;
 457
 458 generate
 459         if (A_SIGNED) begin:BLOCK1
 460                 assign Y = $signed(A) >>> B;
 461         end else begin:BLOCK2
 462                 assign Y = A >>> B;
 463         end
 464 endgenerate
 465
 466 endmodule
 467
 468 // --------------------------------------------------------
 469
 470 module \$shift (A, B, Y);
 471
 472 parameter A_SIGNED = 0;
 473 parameter B_SIGNED = 0;
 474 parameter A_WIDTH = 0;
 475 parameter B_WIDTH = 0;
 476 parameter Y_WIDTH = 0;
 477
 478 input [A_WIDTH-1:0] A;
 479 input [B_WIDTH-1:0] B;
 480 output [Y_WIDTH-1:0] Y;
 481
 482 generate
 483         if (B_SIGNED) begin:BLOCK1
 484                 assign Y = $signed(B) < 0 ? A << -B : A >> B;
 485         end else begin:BLOCK2
 486                 assign Y = A >> B;
 487         end
 488 endgenerate
 489
 490 endmodule
 491
 492 // --------------------------------------------------------
 493
 494 module \$shiftx (A, B, Y);
 495
 496 parameter A_SIGNED = 0;
 497 parameter B_SIGNED = 0;
 498 parameter A_WIDTH = 0;
 499 parameter B_WIDTH = 0;
 500 parameter Y_WIDTH = 0;
 501
 502 input [A_WIDTH-1:0] A;
 503 input [B_WIDTH-1:0] B;
 504 output [Y_WIDTH-1:0] Y;
 505
 506 generate
 507         if (Y_WIDTH > 0)
 508                 if (B_SIGNED) begin:BLOCK1
 509                         assign Y = A[$signed(B) +: Y_WIDTH];
 510                 end else begin:BLOCK2
 511                         assign Y = A[B +: Y_WIDTH];
 512                 end
 513 endgenerate
 514
 515 endmodule
 516
 517 // --------------------------------------------------------
 518
 519 module \$fa (A, B, C, X, Y);
 520
 521 parameter WIDTH = 1;
 522
 523 input [WIDTH-1:0] A, B, C;
 524 output [WIDTH-1:0] X, Y;
 525
 526 wire [WIDTH-1:0] t1, t2, t3;
 527
 528 assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
 529 assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
 530
 531 endmodule
 532
 533 // --------------------------------------------------------
 534
 535 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 536 //-
 537 //-     $lcu (P, G, CI, CO)
 538 //-
 539 //- Lookahead carry unit
 540 //- A building block dedicated to fast computation of carry-bits used in binary
 541 //- arithmetic operations. By replacing the ripple carry structure used in full-adder
 542 //- blocks, the more significant  bits of the sum can be expected to be computed more
 543 //- quickly.
 544 //- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
 545 //- +/techmap.v).
 546 module \$lcu (P, G, CI, CO);
 547
 548 parameter WIDTH = 1;
 549
 550 input [WIDTH-1:0] P;    // Propagate
 551 input [WIDTH-1:0] G;    // Generate
 552 input CI;               // Carry-in
 553
 554 output reg [WIDTH-1:0] CO; // Carry-out
 555
 556 integer i;
 557 always @* begin
 558         CO = 'bx;
 559         if (^{P, G, CI} !== 1'bx) begin
 560                 CO[0] = G[0] || (P[0] && CI);
 561                 for (i = 1; i < WIDTH; i = i+1)
 562                         CO[i] = G[i] || (P[i] && CO[i-1]);
 563         end
 564 end
 565
 566 endmodule
 567
 568 // --------------------------------------------------------
 569
 570 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 571 //-
 572 //-     $alu (A, B, CI, BI, X, Y, CO)
 573 //-
 574 //- Arithmetic logic unit.
 575 //- A building block supporting both binary addition/subtraction operations, and
 576 //- indirectly, comparison operations.
 577 //- Typically created by the `alumacc` pass, which transforms:
 578 //-   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
 579 //- cells into this $alu cell.
 580 //-
 581 module \$alu (A, B, CI, BI, X, Y, CO);
 582
 583 parameter A_SIGNED = 0;
 584 parameter B_SIGNED = 0;
 585 parameter A_WIDTH = 1;
 586 parameter B_WIDTH = 1;
 587 parameter Y_WIDTH = 1;
 588
 589 input [A_WIDTH-1:0] A;      // Input operand
 590 input [B_WIDTH-1:0] B;      // Input operand
 591 output [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,
 592                             //          used in combination with
 593                             //          reduction-AND for $eq/$ne ops)
 594 output [Y_WIDTH-1:0] Y;     // Sum
 595
 596 input CI;                   // Carry-in (set for $sub)
 597 input BI;                   // Invert-B (set for $sub)
 598 output [Y_WIDTH-1:0] CO;    // Carry-out
 599
 600 wire [Y_WIDTH-1:0] AA, BB;
 601
 602 generate
 603         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 604                 assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
 605         end else begin:BLOCK2
 606                 assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
 607         end
 608 endgenerate
 609
 610 // this is 'x' if Y and CO should be all 'x', and '0' otherwise
 611 wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
 612
 613 assign X = AA ^ BB;
 614 // Full adder
 615 assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
 616
 617 function get_carry;
 618         input a, b, c;
 619         get_carry = (a&b) | (a&c) | (b&c);
 620 endfunction
 621
 622 genvar i;
 623 generate
 624         assign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;
 625         for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3
 626                 assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;
 627         end
 628 endgenerate
 629
 630 endmodule
 631
 632 // --------------------------------------------------------
 633
 634 module \$lt (A, B, Y);
 635
 636 parameter A_SIGNED = 0;
 637 parameter B_SIGNED = 0;
 638 parameter A_WIDTH = 0;
 639 parameter B_WIDTH = 0;
 640 parameter Y_WIDTH = 0;
 641
 642 input [A_WIDTH-1:0] A;
 643 input [B_WIDTH-1:0] B;
 644 output [Y_WIDTH-1:0] Y;
 645
 646 generate
 647         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 648                 assign Y = $signed(A) < $signed(B);
 649         end else begin:BLOCK2
 650                 assign Y = A < B;
 651         end
 652 endgenerate
 653
 654 endmodule
 655
 656 // --------------------------------------------------------
 657
 658 module \$le (A, B, Y);
 659
 660 parameter A_SIGNED = 0;
 661 parameter B_SIGNED = 0;
 662 parameter A_WIDTH = 0;
 663 parameter B_WIDTH = 0;
 664 parameter Y_WIDTH = 0;
 665
 666 input [A_WIDTH-1:0] A;
 667 input [B_WIDTH-1:0] B;
 668 output [Y_WIDTH-1:0] Y;
 669
 670 generate
 671         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 672                 assign Y = $signed(A) <= $signed(B);
 673         end else begin:BLOCK2
 674                 assign Y = A <= B;
 675         end
 676 endgenerate
 677
 678 endmodule
 679
 680 // --------------------------------------------------------
 681
 682 module \$eq (A, B, Y);
 683
 684 parameter A_SIGNED = 0;
 685 parameter B_SIGNED = 0;
 686 parameter A_WIDTH = 0;
 687 parameter B_WIDTH = 0;
 688 parameter Y_WIDTH = 0;
 689
 690 input [A_WIDTH-1:0] A;
 691 input [B_WIDTH-1:0] B;
 692 output [Y_WIDTH-1:0] Y;
 693
 694 generate
 695         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 696                 assign Y = $signed(A) == $signed(B);
 697         end else begin:BLOCK2
 698                 assign Y = A == B;
 699         end
 700 endgenerate
 701
 702 endmodule
 703
 704 // --------------------------------------------------------
 705
 706 module \$ne (A, B, Y);
 707
 708 parameter A_SIGNED = 0;
 709 parameter B_SIGNED = 0;
 710 parameter A_WIDTH = 0;
 711 parameter B_WIDTH = 0;
 712 parameter Y_WIDTH = 0;
 713
 714 input [A_WIDTH-1:0] A;
 715 input [B_WIDTH-1:0] B;
 716 output [Y_WIDTH-1:0] Y;
 717
 718 generate
 719         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 720                 assign Y = $signed(A) != $signed(B);
 721         end else begin:BLOCK2
 722                 assign Y = A != B;
 723         end
 724 endgenerate
 725
 726 endmodule
 727
 728 // --------------------------------------------------------
 729
 730 module \$eqx (A, B, Y);
 731
 732 parameter A_SIGNED = 0;
 733 parameter B_SIGNED = 0;
 734 parameter A_WIDTH = 0;
 735 parameter B_WIDTH = 0;
 736 parameter Y_WIDTH = 0;
 737
 738 input [A_WIDTH-1:0] A;
 739 input [B_WIDTH-1:0] B;
 740 output [Y_WIDTH-1:0] Y;
 741
 742 generate
 743         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 744                 assign Y = $signed(A) === $signed(B);
 745         end else begin:BLOCK2
 746                 assign Y = A === B;
 747         end
 748 endgenerate
 749
 750 endmodule
 751
 752 // --------------------------------------------------------
 753
 754 module \$nex (A, B, Y);
 755
 756 parameter A_SIGNED = 0;
 757 parameter B_SIGNED = 0;
 758 parameter A_WIDTH = 0;
 759 parameter B_WIDTH = 0;
 760 parameter Y_WIDTH = 0;
 761
 762 input [A_WIDTH-1:0] A;
 763 input [B_WIDTH-1:0] B;
 764 output [Y_WIDTH-1:0] Y;
 765
 766 generate
 767         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 768                 assign Y = $signed(A) !== $signed(B);
 769         end else begin:BLOCK2
 770                 assign Y = A !== B;
 771         end
 772 endgenerate
 773
 774 endmodule
 775
 776 // --------------------------------------------------------
 777
 778 module \$ge (A, B, Y);
 779
 780 parameter A_SIGNED = 0;
 781 parameter B_SIGNED = 0;
 782 parameter A_WIDTH = 0;
 783 parameter B_WIDTH = 0;
 784 parameter Y_WIDTH = 0;
 785
 786 input [A_WIDTH-1:0] A;
 787 input [B_WIDTH-1:0] B;
 788 output [Y_WIDTH-1:0] Y;
 789
 790 generate
 791         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 792                 assign Y = $signed(A) >= $signed(B);
 793         end else begin:BLOCK2
 794                 assign Y = A >= B;
 795         end
 796 endgenerate
 797
 798 endmodule
 799
 800 // --------------------------------------------------------
 801
 802 module \$gt (A, B, Y);
 803
 804 parameter A_SIGNED = 0;
 805 parameter B_SIGNED = 0;
 806 parameter A_WIDTH = 0;
 807 parameter B_WIDTH = 0;
 808 parameter Y_WIDTH = 0;
 809
 810 input [A_WIDTH-1:0] A;
 811 input [B_WIDTH-1:0] B;
 812 output [Y_WIDTH-1:0] Y;
 813
 814 generate
 815         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 816                 assign Y = $signed(A) > $signed(B);
 817         end else begin:BLOCK2
 818                 assign Y = A > B;
 819         end
 820 endgenerate
 821
 822 endmodule
 823
 824 // --------------------------------------------------------
 825
 826 module \$add (A, B, Y);
 827
 828 parameter A_SIGNED = 0;
 829 parameter B_SIGNED = 0;
 830 parameter A_WIDTH = 0;
 831 parameter B_WIDTH = 0;
 832 parameter Y_WIDTH = 0;
 833
 834 input [A_WIDTH-1:0] A;
 835 input [B_WIDTH-1:0] B;
 836 output [Y_WIDTH-1:0] Y;
 837
 838 generate
 839         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 840                 assign Y = $signed(A) + $signed(B);
 841         end else begin:BLOCK2
 842                 assign Y = A + B;
 843         end
 844 endgenerate
 845
 846 endmodule
 847
 848 // --------------------------------------------------------
 849
 850 module \$sub (A, B, Y);
 851
 852 parameter A_SIGNED = 0;
 853 parameter B_SIGNED = 0;
 854 parameter A_WIDTH = 0;
 855 parameter B_WIDTH = 0;
 856 parameter Y_WIDTH = 0;
 857
 858 input [A_WIDTH-1:0] A;
 859 input [B_WIDTH-1:0] B;
 860 output [Y_WIDTH-1:0] Y;
 861
 862 generate
 863         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 864                 assign Y = $signed(A) - $signed(B);
 865         end else begin:BLOCK2
 866                 assign Y = A - B;
 867         end
 868 endgenerate
 869
 870 endmodule
 871
 872 // --------------------------------------------------------
 873
 874 module \$mul (A, B, Y);
 875
 876 parameter A_SIGNED = 0;
 877 parameter B_SIGNED = 0;
 878 parameter A_WIDTH = 0;
 879 parameter B_WIDTH = 0;
 880 parameter Y_WIDTH = 0;
 881
 882 input [A_WIDTH-1:0] A;
 883 input [B_WIDTH-1:0] B;
 884 output [Y_WIDTH-1:0] Y;
 885
 886 generate
 887         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 888                 assign Y = $signed(A) * $signed(B);
 889         end else begin:BLOCK2
 890                 assign Y = A * B;
 891         end
 892 endgenerate
 893
 894 endmodule
 895
 896 // --------------------------------------------------------
 897
 898 module \$macc (A, B, Y);
 899
 900 parameter A_WIDTH = 0;
 901 parameter B_WIDTH = 0;
 902 parameter Y_WIDTH = 0;
 903 parameter CONFIG = 4'b0000;
 904 parameter CONFIG_WIDTH = 4;
 905
 906 input [A_WIDTH-1:0] A;
 907 input [B_WIDTH-1:0] B;
 908 output reg [Y_WIDTH-1:0] Y;
 909
 910 // Xilinx XSIM does not like $clog2() below..
 911 function integer my_clog2;
 912         input integer v;
 913         begin
 914                 if (v > 0)
 915                         v = v - 1;
 916                 my_clog2 = 0;
 917                 while (v) begin
 918                         v = v >> 1;
 919                         my_clog2 = my_clog2 + 1;
 920                 end
 921         end
 922 endfunction
 923
 924 localparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;
 925 localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
 926 localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;
 927
 928 function [2*num_ports*num_abits-1:0] get_port_offsets;
 929         input [CONFIG_WIDTH-1:0] cfg;
 930         integer i, cursor;
 931         begin
 932                 cursor = 0;
 933                 get_port_offsets = 0;
 934                 for (i = 0; i < num_ports; i = i+1) begin
 935                         get_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;
 936                         cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];
 937                         get_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;
 938                         cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];
 939                 end
 940         end
 941 endfunction
 942
 943 localparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);
 944
 945 `define PORT_IS_SIGNED   (0 + CONFIG[4 + i*(2 + 2*num_bits)])
 946 `define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])
 947 `define PORT_SIZE_A      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])
 948 `define PORT_SIZE_B      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])
 949 `define PORT_OFFSET_A    (0 + port_offsets[2*i*num_abits +: num_abits])
 950 `define PORT_OFFSET_B    (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])
 951
 952 integer i, j;
 953 reg [Y_WIDTH-1:0] tmp_a, tmp_b;
 954
 955 always @* begin
 956         Y = 0;
 957         for (i = 0; i < num_ports; i = i+1)
 958         begin
 959                 tmp_a = 0;
 960                 tmp_b = 0;
 961
 962                 for (j = 0; j < `PORT_SIZE_A; j = j+1)
 963                         tmp_a[j] = A[`PORT_OFFSET_A + j];
 964
 965                 if (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)
 966                         for (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)
 967                                 tmp_a[j] = tmp_a[`PORT_SIZE_A-1];
 968
 969                 for (j = 0; j < `PORT_SIZE_B; j = j+1)
 970                         tmp_b[j] = A[`PORT_OFFSET_B + j];
 971
 972                 if (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)
 973                         for (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)
 974                                 tmp_b[j] = tmp_b[`PORT_SIZE_B-1];
 975
 976                 if (`PORT_SIZE_B > 0)
 977                         tmp_a = tmp_a * tmp_b;
 978
 979                 if (`PORT_DO_SUBTRACT)
 980                         Y = Y - tmp_a;
 981                 else
 982                         Y = Y + tmp_a;
 983         end
 984         for (i = 0; i < B_WIDTH; i = i+1) begin
 985                 Y = Y + B[i];
 986         end
 987 end
 988
 989 `undef PORT_IS_SIGNED
 990 `undef PORT_DO_SUBTRACT
 991 `undef PORT_SIZE_A
 992 `undef PORT_SIZE_B
 993 `undef PORT_OFFSET_A
 994 `undef PORT_OFFSET_B
 995
 996 endmodule
 997
 998 // --------------------------------------------------------
 999
1000 module \$div (A, B, Y);
1001
1002 parameter A_SIGNED = 0;
1003 parameter B_SIGNED = 0;
1004 parameter A_WIDTH = 0;
1005 parameter B_WIDTH = 0;
1006 parameter Y_WIDTH = 0;
1007
1008 input [A_WIDTH-1:0] A;
1009 input [B_WIDTH-1:0] B;
1010 output [Y_WIDTH-1:0] Y;
1011
1012 generate
1013         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1014                 assign Y = $signed(A) / $signed(B);
1015         end else begin:BLOCK2
1016                 assign Y = A / B;
1017         end
1018 endgenerate
1019
1020 endmodule
1021
1022 // --------------------------------------------------------
1023
1024 module \$mod (A, B, Y);
1025
1026 parameter A_SIGNED = 0;
1027 parameter B_SIGNED = 0;
1028 parameter A_WIDTH = 0;
1029 parameter B_WIDTH = 0;
1030 parameter Y_WIDTH = 0;
1031
1032 input [A_WIDTH-1:0] A;
1033 input [B_WIDTH-1:0] B;
1034 output [Y_WIDTH-1:0] Y;
1035
1036 generate
1037         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1038                 assign Y = $signed(A) % $signed(B);
1039         end else begin:BLOCK2
1040                 assign Y = A % B;
1041         end
1042 endgenerate
1043
1044 endmodule
1045
1046 // --------------------------------------------------------
1047 `ifndef SIMLIB_NOPOW
1048
1049 module \$pow (A, B, Y);
1050
1051 parameter A_SIGNED = 0;
1052 parameter B_SIGNED = 0;
1053 parameter A_WIDTH = 0;
1054 parameter B_WIDTH = 0;
1055 parameter Y_WIDTH = 0;
1056
1057 input [A_WIDTH-1:0] A;
1058 input [B_WIDTH-1:0] B;
1059 output [Y_WIDTH-1:0] Y;
1060
1061 generate
1062         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1063                 assign Y = $signed(A) ** $signed(B);
1064         end else if (A_SIGNED) begin:BLOCK2
1065                 assign Y = $signed(A) ** B;
1066         end else if (B_SIGNED) begin:BLOCK3
1067                 assign Y = A ** $signed(B);
1068         end else begin:BLOCK4
1069                 assign Y = A ** B;
1070         end
1071 endgenerate
1072
1073 endmodule
1074
1075 `endif
1076 // --------------------------------------------------------
1077
1078 module \$logic_not (A, Y);
1079
1080 parameter A_SIGNED = 0;
1081 parameter A_WIDTH = 0;
1082 parameter Y_WIDTH = 0;
1083
1084 input [A_WIDTH-1:0] A;
1085 output [Y_WIDTH-1:0] Y;
1086
1087 generate
1088         if (A_SIGNED) begin:BLOCK1
1089                 assign Y = !$signed(A);
1090         end else begin:BLOCK2
1091                 assign Y = !A;
1092         end
1093 endgenerate
1094
1095 endmodule
1096
1097 // --------------------------------------------------------
1098
1099 module \$logic_and (A, B, Y);
1100
1101 parameter A_SIGNED = 0;
1102 parameter B_SIGNED = 0;
1103 parameter A_WIDTH = 0;
1104 parameter B_WIDTH = 0;
1105 parameter Y_WIDTH = 0;
1106
1107 input [A_WIDTH-1:0] A;
1108 input [B_WIDTH-1:0] B;
1109 output [Y_WIDTH-1:0] Y;
1110
1111 generate
1112         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1113                 assign Y = $signed(A) && $signed(B);
1114         end else begin:BLOCK2
1115                 assign Y = A && B;
1116         end
1117 endgenerate
1118
1119 endmodule
1120
1121 // --------------------------------------------------------
1122
1123 module \$logic_or (A, B, Y);
1124
1125 parameter A_SIGNED = 0;
1126 parameter B_SIGNED = 0;
1127 parameter A_WIDTH = 0;
1128 parameter B_WIDTH = 0;
1129 parameter Y_WIDTH = 0;
1130
1131 input [A_WIDTH-1:0] A;
1132 input [B_WIDTH-1:0] B;
1133 output [Y_WIDTH-1:0] Y;
1134
1135 generate
1136         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1137                 assign Y = $signed(A) || $signed(B);
1138         end else begin:BLOCK2
1139                 assign Y = A || B;
1140         end
1141 endgenerate
1142
1143 endmodule
1144
1145 // --------------------------------------------------------
1146
1147 module \$slice (A, Y);
1148
1149 parameter OFFSET = 0;
1150 parameter A_WIDTH = 0;
1151 parameter Y_WIDTH = 0;
1152
1153 input [A_WIDTH-1:0] A;
1154 output [Y_WIDTH-1:0] Y;
1155
1156 assign Y = A >> OFFSET;
1157
1158 endmodule
1159
1160 // --------------------------------------------------------
1161
1162 module \$concat (A, B, Y);
1163
1164 parameter A_WIDTH = 0;
1165 parameter B_WIDTH = 0;
1166
1167 input [A_WIDTH-1:0] A;
1168 input [B_WIDTH-1:0] B;
1169 output [A_WIDTH+B_WIDTH-1:0] Y;
1170
1171 assign Y = {B, A};
1172
1173 endmodule
1174
1175 // --------------------------------------------------------
1176
1177 module \$mux (A, B, S, Y);
1178
1179 parameter WIDTH = 0;
1180
1181 input [WIDTH-1:0] A, B;
1182 input S;
1183 output reg [WIDTH-1:0] Y;
1184
1185 always @* begin
1186         if (S)
1187                 Y = B;
1188         else
1189                 Y = A;
1190 end
1191
1192 endmodule
1193
1194 // --------------------------------------------------------
1195
1196 module \$pmux (A, B, S, Y);
1197
1198 parameter WIDTH = 0;
1199 parameter S_WIDTH = 0;
1200
1201 input [WIDTH-1:0] A;
1202 input [WIDTH*S_WIDTH-1:0] B;
1203 input [S_WIDTH-1:0] S;
1204 output reg [WIDTH-1:0] Y;
1205
1206 integer i;
1207 reg found_active_sel_bit;
1208
1209 always @* begin
1210         Y = A;
1211         found_active_sel_bit = 0;
1212         for (i = 0; i < S_WIDTH; i = i+1)
1213                 if (S[i]) begin
1214                         Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i);
1215                         found_active_sel_bit = 1;
1216                 end
1217 end
1218
1219 endmodule
1220
1221 // --------------------------------------------------------
1222 `ifndef SIMLIB_NOLUT
1223
1224 module \$lut (A, Y);
1225
1226 parameter WIDTH = 0;
1227 parameter LUT = 0;
1228
1229 input [WIDTH-1:0] A;
1230 output reg Y;
1231
1232 wire lut0_out, lut1_out;
1233
1234 generate
1235         if (WIDTH <= 1) begin:simple
1236                 assign {lut1_out, lut0_out} = LUT;
1237         end else begin:complex
1238                 \$lut #( .WIDTH(WIDTH-1), .LUT(LUT                  ) ) lut0 ( .A(A[WIDTH-2:0]), .Y(lut0_out) );
1239                 \$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .A(A[WIDTH-2:0]), .Y(lut1_out) );
1240         end
1241
1242         if (WIDTH > 0) begin:lutlogic
1243                 always @* begin
1244                         casez ({A[WIDTH-1], lut0_out, lut1_out})
1245                                 3'b?11: Y = 1'b1;
1246                                 3'b?00: Y = 1'b0;
1247                                 3'b0??: Y = lut0_out;
1248                                 3'b1??: Y = lut1_out;
1249                                 default: Y = 1'bx;
1250                         endcase
1251                 end
1252         end
1253 endgenerate
1254
1255 endmodule
1256
1257 `endif
1258 // --------------------------------------------------------
1259
1260 module \$sop (A, Y);
1261
1262 parameter WIDTH = 0;
1263 parameter DEPTH = 0;
1264 parameter TABLE = 0;
1265
1266 input [WIDTH-1:0] A;
1267 output reg Y;
1268
1269 integer i, j;
1270 reg match;
1271
1272 always @* begin
1273         Y = 0;
1274         for (i = 0; i < DEPTH; i=i+1) begin
1275                 match = 1;
1276                 for (j = 0; j < WIDTH; j=j+1) begin
1277                         if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
1278                         if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
1279                 end
1280                 if (match) Y = 1;
1281         end
1282 end
1283
1284 endmodule
1285
1286 // --------------------------------------------------------
1287
1288 module \$tribuf (A, EN, Y);
1289
1290 parameter WIDTH = 0;
1291
1292 input [WIDTH-1:0] A;
1293 input EN;
1294 output [WIDTH-1:0] Y;
1295
1296 assign Y = EN ? A : 'bz;
1297
1298 endmodule
1299
1300 // --------------------------------------------------------
1301
1302 module \$specify2 (EN, SRC, DST);
1303
1304 parameter FULL = 0;
1305 parameter SRC_WIDTH = 1;
1306 parameter DST_WIDTH = 1;
1307
1308 parameter SRC_DST_PEN = 0;
1309 parameter SRC_DST_POL = 0;
1310
1311 parameter T_RISE_MIN = 0;
1312 parameter T_RISE_TYP = 0;
1313 parameter T_RISE_MAX = 0;
1314
1315 parameter T_FALL_MIN = 0;
1316 parameter T_FALL_TYP = 0;
1317 parameter T_FALL_MAX = 0;
1318
1319 input EN;
1320 input [SRC_WIDTH-1:0] SRC;
1321 input [DST_WIDTH-1:0] DST;
1322
1323 localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
1324
1325 `ifdef SIMLIB_SPECIFY
1326 specify
1327         if (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1328         if (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1329         if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1330         if (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1331         if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1332         if (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1333 endspecify
1334 `endif
1335
1336 endmodule
1337
1338 // --------------------------------------------------------
1339
1340 module \$specify3 (EN, SRC, DST, DAT);
1341
1342 parameter FULL = 0;
1343 parameter SRC_WIDTH = 1;
1344 parameter DST_WIDTH = 1;
1345
1346 parameter EDGE_EN = 0;
1347 parameter EDGE_POL = 0;
1348
1349 parameter SRC_DST_PEN = 0;
1350 parameter SRC_DST_POL = 0;
1351
1352 parameter DAT_DST_PEN = 0;
1353 parameter DAT_DST_POL = 0;
1354
1355 parameter T_RISE_MIN = 0;
1356 parameter T_RISE_TYP = 0;
1357 parameter T_RISE_MAX = 0;
1358
1359 parameter T_FALL_MIN = 0;
1360 parameter T_FALL_TYP = 0;
1361 parameter T_FALL_MAX = 0;
1362
1363 input EN;
1364 input [SRC_WIDTH-1:0] SRC;
1365 input [DST_WIDTH-1:0] DST, DAT;
1366
1367 localparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;
1368 localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
1369 localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
1370
1371 `ifdef SIMLIB_SPECIFY
1372 specify
1373         // DD=0
1374
1375         if (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1376         if (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1377         if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1378         if (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1379         if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1380         if (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1381
1382         if (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1383         if (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1384         if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1385         if (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1386         if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1387         if (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1388
1389         if (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1390         if (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1391         if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1392         if (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1393         if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1394         if (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1395
1396         // DD=1
1397
1398         if (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1399         if (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1400         if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1401         if (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1402         if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1403         if (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1404
1405         if (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1406         if (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1407         if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1408         if (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1409         if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1410         if (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1411
1412         if (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1413         if (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1414         if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1415         if (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1416         if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1417         if (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1418
1419         // DD=2
1420
1421         if (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1422         if (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1423         if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1424         if (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1425         if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1426         if (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1427
1428         if (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1429         if (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1430         if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1431         if (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1432         if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1433         if (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1434
1435         if (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1436         if (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1437         if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1438         if (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1439         if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1440         if (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1441 endspecify
1442 `endif
1443
1444 endmodule
1445
1446 // --------------------------------------------------------
1447
1448 module \$specrule (EN_SRC, EN_DST, SRC, DST);
1449
1450 parameter TYPE = "";
1451 parameter T_LIMIT = 0;
1452 parameter T_LIMIT2 = 0;
1453
1454 parameter SRC_WIDTH = 1;
1455 parameter DST_WIDTH = 1;
1456
1457 parameter SRC_PEN = 0;
1458 parameter SRC_POL = 0;
1459
1460 parameter DST_PEN = 0;
1461 parameter DST_POL = 0;
1462
1463 input EN_SRC, EN_DST;
1464 input [SRC_WIDTH-1:0] SRC;
1465 input [DST_WIDTH-1:0] DST;
1466
1467 `ifdef SIMLIB_SPECIFY
1468 specify
1469         // TBD
1470 endspecify
1471 `endif
1472
1473 endmodule
1474
1475 // --------------------------------------------------------
1476
1477 module \$assert (A, EN);
1478
1479 input A, EN;
1480
1481 `ifndef SIMLIB_NOCHECKS
1482 always @* begin
1483         if (A !== 1'b1 && EN === 1'b1) begin
1484                 $display("Assertion %m failed!");
1485                 $stop;
1486         end
1487 end
1488 `endif
1489
1490 endmodule
1491
1492 // --------------------------------------------------------
1493
1494 module \$assume (A, EN);
1495
1496 input A, EN;
1497
1498 `ifndef SIMLIB_NOCHECKS
1499 always @* begin
1500         if (A !== 1'b1 && EN === 1'b1) begin
1501                 $display("Assumption %m failed!");
1502                 $stop;
1503         end
1504 end
1505 `endif
1506
1507 endmodule
1508
1509 // --------------------------------------------------------
1510
1511 module \$live (A, EN);
1512
1513 input A, EN;
1514
1515 endmodule
1516
1517 // --------------------------------------------------------
1518
1519 module \$fair (A, EN);
1520
1521 input A, EN;
1522
1523 endmodule
1524
1525 // --------------------------------------------------------
1526
1527 module \$cover (A, EN);
1528
1529 input A, EN;
1530
1531 endmodule
1532
1533 // --------------------------------------------------------
1534
1535 module \$initstate (Y);
1536
1537 output reg Y = 1;
1538 reg [3:0] cnt = 1;
1539 reg trig = 0;
1540
1541 initial trig <= 1;
1542
1543 always @(cnt, trig) begin
1544         Y <= |cnt;
1545         cnt <= cnt + |cnt;
1546 end
1547
1548 endmodule
1549
1550 // --------------------------------------------------------
1551
1552 module \$anyconst (Y);
1553
1554 parameter WIDTH = 0;
1555
1556 output [WIDTH-1:0] Y;
1557
1558 assign Y = 'bx;
1559
1560 endmodule
1561
1562 // --------------------------------------------------------
1563
1564 module \$anyseq (Y);
1565
1566 parameter WIDTH = 0;
1567
1568 output [WIDTH-1:0] Y;
1569
1570 assign Y = 'bx;
1571
1572 endmodule
1573
1574 // --------------------------------------------------------
1575
1576 module \$allconst (Y);
1577
1578 parameter WIDTH = 0;
1579
1580 output [WIDTH-1:0] Y;
1581
1582 assign Y = 'bx;
1583
1584 endmodule
1585
1586 // --------------------------------------------------------
1587
1588 module \$allseq (Y);
1589
1590 parameter WIDTH = 0;
1591
1592 output [WIDTH-1:0] Y;
1593
1594 assign Y = 'bx;
1595
1596 endmodule
1597
1598 // --------------------------------------------------------
1599
1600 module \$equiv (A, B, Y);
1601
1602 input A, B;
1603 output Y;
1604
1605 assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
1606
1607 `ifndef SIMLIB_NOCHECKS
1608 always @* begin
1609         if (A !== 1'bx && A !== B) begin
1610                 $display("Equivalence failed!");
1611                 $stop;
1612         end
1613 end
1614 `endif
1615
1616 endmodule
1617
1618 // --------------------------------------------------------
1619 `ifndef SIMLIB_NOSR
1620
1621 module \$sr (SET, CLR, Q);
1622
1623 parameter WIDTH = 0;
1624 parameter SET_POLARITY = 1'b1;
1625 parameter CLR_POLARITY = 1'b1;
1626
1627 input [WIDTH-1:0] SET, CLR;
1628 output reg [WIDTH-1:0] Q;
1629
1630 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
1631 wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
1632
1633 genvar i;
1634 generate
1635         for (i = 0; i < WIDTH; i = i+1) begin:bitslices
1636                 always @*
1637                         if (pos_clr[i])
1638                                 Q[i] <= 0;
1639                         else if (pos_set[i])
1640                                 Q[i] <= 1;
1641         end
1642 endgenerate
1643
1644 endmodule
1645
1646 `endif
1647 // --------------------------------------------------------
1648 `ifdef SIMLIB_FF
1649
1650 module \$ff (D, Q);
1651
1652 parameter WIDTH = 0;
1653
1654 input [WIDTH-1:0] D;
1655 output reg [WIDTH-1:0] Q;
1656
1657 always @($global_clk) begin
1658         Q <= D;
1659 end
1660
1661 endmodule
1662
1663 `endif
1664 // --------------------------------------------------------
1665
1666 module \$dff (CLK, D, Q);
1667
1668 parameter WIDTH = 0;
1669 parameter CLK_POLARITY = 1'b1;
1670
1671 input CLK;
1672 input [WIDTH-1:0] D;
1673 output reg [WIDTH-1:0] Q;
1674 wire pos_clk = CLK == CLK_POLARITY;
1675
1676 always @(posedge pos_clk) begin
1677         Q <= D;
1678 end
1679
1680 endmodule
1681
1682 // --------------------------------------------------------
1683
1684 module \$dffe (CLK, EN, D, Q);
1685
1686 parameter WIDTH = 0;
1687 parameter CLK_POLARITY = 1'b1;
1688 parameter EN_POLARITY = 1'b1;
1689
1690 input CLK, EN;
1691 input [WIDTH-1:0] D;
1692 output reg [WIDTH-1:0] Q;
1693 wire pos_clk = CLK == CLK_POLARITY;
1694
1695 always @(posedge pos_clk) begin
1696         if (EN == EN_POLARITY) Q <= D;
1697 end
1698
1699 endmodule
1700
1701 // --------------------------------------------------------
1702 `ifndef SIMLIB_NOSR
1703
1704 module \$dffsr (CLK, SET, CLR, D, Q);
1705
1706 parameter WIDTH = 0;
1707 parameter CLK_POLARITY = 1'b1;
1708 parameter SET_POLARITY = 1'b1;
1709 parameter CLR_POLARITY = 1'b1;
1710
1711 input CLK;
1712 input [WIDTH-1:0] SET, CLR, D;
1713 output reg [WIDTH-1:0] Q;
1714
1715 wire pos_clk = CLK == CLK_POLARITY;
1716 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
1717 wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
1718
1719 genvar i;
1720 generate
1721         for (i = 0; i < WIDTH; i = i+1) begin:bitslices
1722                 always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
1723                         if (pos_clr[i])
1724                                 Q[i] <= 0;
1725                         else if (pos_set[i])
1726                                 Q[i] <= 1;
1727                         else
1728                                 Q[i] <= D[i];
1729         end
1730 endgenerate
1731
1732 endmodule
1733
1734 `endif
1735 // --------------------------------------------------------
1736
1737 module \$adff (CLK, ARST, D, Q);
1738
1739 parameter WIDTH = 0;
1740 parameter CLK_POLARITY = 1'b1;
1741 parameter ARST_POLARITY = 1'b1;
1742 parameter ARST_VALUE = 0;
1743
1744 input CLK, ARST;
1745 input [WIDTH-1:0] D;
1746 output reg [WIDTH-1:0] Q;
1747 wire pos_clk = CLK == CLK_POLARITY;
1748 wire pos_arst = ARST == ARST_POLARITY;
1749
1750 always @(posedge pos_clk, posedge pos_arst) begin
1751         if (pos_arst)
1752                 Q <= ARST_VALUE;
1753         else
1754                 Q <= D;
1755 end
1756
1757 endmodule
1758
1759 // --------------------------------------------------------
1760
1761 module \$dlatch (EN, D, Q);
1762
1763 parameter WIDTH = 0;
1764 parameter EN_POLARITY = 1'b1;
1765
1766 input EN;
1767 input [WIDTH-1:0] D;
1768 output reg [WIDTH-1:0] Q;
1769
1770 always @* begin
1771         if (EN == EN_POLARITY)
1772                 Q = D;
1773 end
1774
1775 endmodule
1776
1777 // --------------------------------------------------------
1778 `ifndef SIMLIB_NOSR
1779
1780 module \$dlatchsr (EN, SET, CLR, D, Q);
1781
1782 parameter WIDTH = 0;
1783 parameter EN_POLARITY = 1'b1;
1784 parameter SET_POLARITY = 1'b1;
1785 parameter CLR_POLARITY = 1'b1;
1786
1787 input EN;
1788 input [WIDTH-1:0] SET, CLR, D;
1789 output reg [WIDTH-1:0] Q;
1790
1791 wire pos_en = EN == EN_POLARITY;
1792 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
1793 wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
1794
1795 genvar i;
1796 generate
1797         for (i = 0; i < WIDTH; i = i+1) begin:bitslices
1798                 always @*
1799                         if (pos_clr[i])
1800                                 Q[i] = 0;
1801                         else if (pos_set[i])
1802                                 Q[i] = 1;
1803                         else if (pos_en)
1804                                 Q[i] = D[i];
1805         end
1806 endgenerate
1807
1808 endmodule
1809
1810 `endif
1811 // --------------------------------------------------------
1812
1813 module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
1814
1815 parameter NAME = "";
1816
1817 parameter CLK_POLARITY = 1'b1;
1818 parameter ARST_POLARITY = 1'b1;
1819
1820 parameter CTRL_IN_WIDTH = 1;
1821 parameter CTRL_OUT_WIDTH = 1;
1822
1823 parameter STATE_BITS = 1;
1824 parameter STATE_NUM = 1;
1825 parameter STATE_NUM_LOG2 = 1;
1826 parameter STATE_RST = 0;
1827 parameter STATE_TABLE = 1'b0;
1828
1829 parameter TRANS_NUM = 1;
1830 parameter TRANS_TABLE = 4'b0x0x;
1831
1832 input CLK, ARST;
1833 input [CTRL_IN_WIDTH-1:0] CTRL_IN;
1834 output reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;
1835
1836 wire pos_clk = CLK == CLK_POLARITY;
1837 wire pos_arst = ARST == ARST_POLARITY;
1838
1839 reg [STATE_BITS-1:0] state;
1840 reg [STATE_BITS-1:0] state_tmp;
1841 reg [STATE_BITS-1:0] next_state;
1842
1843 reg [STATE_BITS-1:0] tr_state_in;
1844 reg [STATE_BITS-1:0] tr_state_out;
1845 reg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;
1846 reg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;
1847
1848 integer i;
1849
1850 task tr_fetch;
1851         input [31:0] tr_num;
1852         reg [31:0] tr_pos;
1853         reg [STATE_NUM_LOG2-1:0] state_num;
1854         begin
1855                 tr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;
1856                 tr_ctrl_out = TRANS_TABLE >> tr_pos;
1857                 tr_pos = tr_pos + CTRL_OUT_WIDTH;
1858                 state_num = TRANS_TABLE >> tr_pos;
1859                 tr_state_out = STATE_TABLE >> (STATE_BITS*state_num);
1860                 tr_pos = tr_pos + STATE_NUM_LOG2;
1861                 tr_ctrl_in = TRANS_TABLE >> tr_pos;
1862                 tr_pos = tr_pos + CTRL_IN_WIDTH;
1863                 state_num = TRANS_TABLE >> tr_pos;
1864                 tr_state_in = STATE_TABLE >> (STATE_BITS*state_num);
1865                 tr_pos = tr_pos + STATE_NUM_LOG2;
1866         end
1867 endtask
1868
1869 always @(posedge pos_clk, posedge pos_arst) begin
1870         if (pos_arst) begin
1871                 state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
1872                 for (i = 0; i < STATE_BITS; i = i+1)
1873                         if (state_tmp[i] === 1'bz)
1874                                 state_tmp[i] = 0;
1875                 state <= state_tmp;
1876         end else begin
1877                 state_tmp = next_state;
1878                 for (i = 0; i < STATE_BITS; i = i+1)
1879                         if (state_tmp[i] === 1'bz)
1880                                 state_tmp[i] = 0;
1881                 state <= state_tmp;
1882         end
1883 end
1884
1885 always @(state, CTRL_IN) begin
1886         next_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
1887         CTRL_OUT <= 'bx;
1888         // $display("---");
1889         // $display("Q: %b %b", state, CTRL_IN);
1890         for (i = 0; i < TRANS_NUM; i = i+1) begin
1891                 tr_fetch(i);
1892                 // $display("T: %b %b -> %b %b [%d]", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);
1893                 casez ({state, CTRL_IN})
1894                         {tr_state_in, tr_ctrl_in}: begin
1895                                 // $display("-> %b %b <-   MATCH", state, CTRL_IN);
1896                                 {next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};
1897                         end
1898                 endcase
1899         end
1900 end
1901
1902 endmodule
1903
1904 // --------------------------------------------------------
1905 `ifndef SIMLIB_NOMEM
1906
1907 module \$memrd (CLK, EN, ADDR, DATA);
1908
1909 parameter MEMID = "";
1910 parameter ABITS = 8;
1911 parameter WIDTH = 8;
1912
1913 parameter CLK_ENABLE = 0;
1914 parameter CLK_POLARITY = 0;
1915 parameter TRANSPARENT = 0;
1916
1917 input CLK, EN;
1918 input [ABITS-1:0] ADDR;
1919 output [WIDTH-1:0] DATA;
1920
1921 initial begin
1922         if (MEMID != "") begin
1923                 $display("ERROR: Found non-simulatable instance of $memrd!");
1924                 $finish;
1925         end
1926 end
1927
1928 endmodule
1929
1930 // --------------------------------------------------------
1931
1932 module \$memwr (CLK, EN, ADDR, DATA);
1933
1934 parameter MEMID = "";
1935 parameter ABITS = 8;
1936 parameter WIDTH = 8;
1937
1938 parameter CLK_ENABLE = 0;
1939 parameter CLK_POLARITY = 0;
1940 parameter PRIORITY = 0;
1941
1942 input CLK;
1943 input [WIDTH-1:0] EN;
1944 input [ABITS-1:0] ADDR;
1945 input [WIDTH-1:0] DATA;
1946
1947 initial begin
1948         if (MEMID != "") begin
1949                 $display("ERROR: Found non-simulatable instance of $memwr!");
1950                 $finish;
1951         end
1952 end
1953
1954 endmodule
1955
1956 // --------------------------------------------------------
1957
1958 module \$meminit (ADDR, DATA);
1959
1960 parameter MEMID = "";
1961 parameter ABITS = 8;
1962 parameter WIDTH = 8;
1963 parameter WORDS = 1;
1964
1965 parameter PRIORITY = 0;
1966
1967 input [ABITS-1:0] ADDR;
1968 input [WORDS*WIDTH-1:0] DATA;
1969
1970 initial begin
1971         if (MEMID != "") begin
1972                 $display("ERROR: Found non-simulatable instance of $meminit!");
1973                 $finish;
1974         end
1975 end
1976
1977 endmodule
1978
1979 // --------------------------------------------------------
1980
1981 module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
1982
1983 parameter MEMID = "";
1984 parameter signed SIZE = 4;
1985 parameter signed OFFSET = 0;
1986 parameter signed ABITS = 2;
1987 parameter signed WIDTH = 8;
1988 parameter signed INIT = 1'bx;
1989
1990 parameter signed RD_PORTS = 1;
1991 parameter RD_CLK_ENABLE = 1'b1;
1992 parameter RD_CLK_POLARITY = 1'b1;
1993 parameter RD_TRANSPARENT = 1'b1;
1994
1995 parameter signed WR_PORTS = 1;
1996 parameter WR_CLK_ENABLE = 1'b1;
1997 parameter WR_CLK_POLARITY = 1'b1;
1998
1999 input [RD_PORTS-1:0] RD_CLK;
2000 input [RD_PORTS-1:0] RD_EN;
2001 input [RD_PORTS*ABITS-1:0] RD_ADDR;
2002 output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
2003
2004 input [WR_PORTS-1:0] WR_CLK;
2005 input [WR_PORTS*WIDTH-1:0] WR_EN;
2006 input [WR_PORTS*ABITS-1:0] WR_ADDR;
2007 input [WR_PORTS*WIDTH-1:0] WR_DATA;
2008
2009 reg [WIDTH-1:0] memory [SIZE-1:0];
2010
2011 integer i, j;
2012 reg [WR_PORTS-1:0] LAST_WR_CLK;
2013 reg [RD_PORTS-1:0] LAST_RD_CLK;
2014
2015 function port_active;
2016         input clk_enable;
2017         input clk_polarity;
2018         input last_clk;
2019         input this_clk;
2020         begin
2021                 casez ({clk_enable, clk_polarity, last_clk, this_clk})
2022                         4'b0???: port_active = 1;
2023                         4'b1101: port_active = 1;
2024                         4'b1010: port_active = 1;
2025                         default: port_active = 0;
2026                 endcase
2027         end
2028 endfunction
2029
2030 initial begin
2031         for (i = 0; i < SIZE; i = i+1)
2032                 memory[i] = INIT >>> (i*WIDTH);
2033 end
2034
2035 always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
2036 `ifdef SIMLIB_MEMDELAY
2037         #`SIMLIB_MEMDELAY;
2038 `endif
2039         for (i = 0; i < RD_PORTS; i = i+1) begin
2040                 if (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
2041                         // $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
2042                         RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
2043                 end
2044         end
2045
2046         for (i = 0; i < WR_PORTS; i = i+1) begin
2047                 if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
2048                         for (j = 0; j < WIDTH; j = j+1)
2049                                 if (WR_EN[i*WIDTH+j]) begin
2050                                         // $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
2051                                         memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
2052                                 end
2053         end
2054
2055         for (i = 0; i < RD_PORTS; i = i+1) begin
2056                 if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
2057                         // $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
2058                         RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
2059                 end
2060         end
2061
2062         LAST_RD_CLK <= RD_CLK;
2063         LAST_WR_CLK <= WR_CLK;
2064 end
2065
2066 endmodule
2067
2068 `endif
2069
2070 // --------------------------------------------------------