techlibs/common/simlib.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Simulation Library.
  21  *
  22  *  This Verilog library contains simple simulation models for the internal
  23  *  cells ($not, ...) generated by the frontends and used in most passes.
  24  *
  25  *  This library can be used to verify the internal netlists as generated
  26  *  by the different frontends and passes.
  27  *
  28  *  Note that memory can only be simulated when all $memrd and $memwr cells
  29  *  have been merged to stand-alone $mem cells (this is what the "memory_collect"
  30  *  pass is doing).
  31  *
  32  */
  33
  34 // --------------------------------------------------------
  35
  36 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  37 //-
  38 //-     $not (A, Y)
  39 //-
  40 //- A bit-wise inverter. This corresponds to the Verilog unary prefix '~' operator.
  41 //-
  42 module \$not (A, Y);
  43
  44 parameter A_SIGNED = 0;
  45 parameter A_WIDTH = 0;
  46 parameter Y_WIDTH = 0;
  47
  48 input [A_WIDTH-1:0] A;
  49 output [Y_WIDTH-1:0] Y;
  50
  51 generate
  52         if (A_SIGNED) begin:BLOCK1
  53                 assign Y = ~$signed(A);
  54         end else begin:BLOCK2
  55                 assign Y = ~A;
  56         end
  57 endgenerate
  58
  59 endmodule
  60
  61
  62 // --------------------------------------------------------
  63
  64 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  65 //-
  66 //-     $pos (A, Y)
  67 //-
  68 //- A buffer. This corresponds to the Verilog unary prefix '+' operator.
  69 //-
  70 module \$pos (A, Y);
  71
  72 parameter A_SIGNED = 0;
  73 parameter A_WIDTH = 0;
  74 parameter Y_WIDTH = 0;
  75
  76 input [A_WIDTH-1:0] A;
  77 output [Y_WIDTH-1:0] Y;
  78
  79 generate
  80         if (A_SIGNED) begin:BLOCK1
  81                 assign Y = $signed(A);
  82         end else begin:BLOCK2
  83                 assign Y = A;
  84         end
  85 endgenerate
  86
  87 endmodule
  88
  89 // --------------------------------------------------------
  90
  91 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  92 //-
  93 //-     $neg (A, Y)
  94 //-
  95 //- An arithmetic inverter. This corresponds to the Verilog unary prefix '-' operator.
  96 //-
  97 module \$neg (A, Y);
  98
  99 parameter A_SIGNED = 0;
 100 parameter A_WIDTH = 0;
 101 parameter Y_WIDTH = 0;
 102
 103 input [A_WIDTH-1:0] A;
 104 output [Y_WIDTH-1:0] Y;
 105
 106 generate
 107         if (A_SIGNED) begin:BLOCK1
 108                 assign Y = -$signed(A);
 109         end else begin:BLOCK2
 110                 assign Y = -A;
 111         end
 112 endgenerate
 113
 114 endmodule
 115
 116 // --------------------------------------------------------
 117
 118 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 119 //-
 120 //-     $and (A, B, Y)
 121 //-
 122 //- A bit-wise AND. This corresponds to the Verilog '&' operator.
 123 //-
 124 module \$and (A, B, Y);
 125
 126 parameter A_SIGNED = 0;
 127 parameter B_SIGNED = 0;
 128 parameter A_WIDTH = 0;
 129 parameter B_WIDTH = 0;
 130 parameter Y_WIDTH = 0;
 131
 132 input [A_WIDTH-1:0] A;
 133 input [B_WIDTH-1:0] B;
 134 output [Y_WIDTH-1:0] Y;
 135
 136 generate
 137         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 138                 assign Y = $signed(A) & $signed(B);
 139         end else begin:BLOCK2
 140                 assign Y = A & B;
 141         end
 142 endgenerate
 143
 144 endmodule
 145
 146 // --------------------------------------------------------
 147
 148 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 149 //-
 150 //-     $or (A, B, Y)
 151 //-
 152 //- A bit-wise OR. This corresponds to the Verilog '|' operator.
 153 //-
 154 module \$or (A, B, Y);
 155
 156 parameter A_SIGNED = 0;
 157 parameter B_SIGNED = 0;
 158 parameter A_WIDTH = 0;
 159 parameter B_WIDTH = 0;
 160 parameter Y_WIDTH = 0;
 161
 162 input [A_WIDTH-1:0] A;
 163 input [B_WIDTH-1:0] B;
 164 output [Y_WIDTH-1:0] Y;
 165
 166 generate
 167         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 168                 assign Y = $signed(A) | $signed(B);
 169         end else begin:BLOCK2
 170                 assign Y = A | B;
 171         end
 172 endgenerate
 173
 174 endmodule
 175
 176 // --------------------------------------------------------
 177
 178 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 179 //-
 180 //-     $xor (A, B, Y)
 181 //-
 182 //- A bit-wise XOR. This corresponds to the Verilog '^' operator.
 183 //-
 184 module \$xor (A, B, Y);
 185
 186 parameter A_SIGNED = 0;
 187 parameter B_SIGNED = 0;
 188 parameter A_WIDTH = 0;
 189 parameter B_WIDTH = 0;
 190 parameter Y_WIDTH = 0;
 191
 192 input [A_WIDTH-1:0] A;
 193 input [B_WIDTH-1:0] B;
 194 output [Y_WIDTH-1:0] Y;
 195
 196 generate
 197         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 198                 assign Y = $signed(A) ^ $signed(B);
 199         end else begin:BLOCK2
 200                 assign Y = A ^ B;
 201         end
 202 endgenerate
 203
 204 endmodule
 205
 206 // --------------------------------------------------------
 207
 208 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 209 //-
 210 //-     $xnor (A, B, Y)
 211 //-
 212 //- A bit-wise XNOR. This corresponds to the Verilog '~^' operator.
 213 //-
 214 module \$xnor (A, B, Y);
 215
 216 parameter A_SIGNED = 0;
 217 parameter B_SIGNED = 0;
 218 parameter A_WIDTH = 0;
 219 parameter B_WIDTH = 0;
 220 parameter Y_WIDTH = 0;
 221
 222 input [A_WIDTH-1:0] A;
 223 input [B_WIDTH-1:0] B;
 224 output [Y_WIDTH-1:0] Y;
 225
 226 generate
 227         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 228                 assign Y = $signed(A) ~^ $signed(B);
 229         end else begin:BLOCK2
 230                 assign Y = A ~^ B;
 231         end
 232 endgenerate
 233
 234 endmodule
 235
 236 // --------------------------------------------------------
 237
 238 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 239 //-
 240 //-     $reduce_and (A, B, Y)
 241 //-
 242 //- An AND reduction. This corresponds to the Verilog unary prefix '&' operator.
 243 //-
 244 module \$reduce_and (A, Y);
 245
 246 parameter A_SIGNED = 0;
 247 parameter A_WIDTH = 0;
 248 parameter Y_WIDTH = 0;
 249
 250 input [A_WIDTH-1:0] A;
 251 output [Y_WIDTH-1:0] Y;
 252
 253 generate
 254         if (A_SIGNED) begin:BLOCK1
 255                 assign Y = &$signed(A);
 256         end else begin:BLOCK2
 257                 assign Y = &A;
 258         end
 259 endgenerate
 260
 261 endmodule
 262
 263 // --------------------------------------------------------
 264
 265 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 266 //-
 267 //-     $reduce_or (A, B, Y)
 268 //-
 269 //- An OR reduction. This corresponds to the Verilog unary prefix '|' operator.
 270 //-
 271 module \$reduce_or (A, Y);
 272
 273 parameter A_SIGNED = 0;
 274 parameter A_WIDTH = 0;
 275 parameter Y_WIDTH = 0;
 276
 277 input [A_WIDTH-1:0] A;
 278 output [Y_WIDTH-1:0] Y;
 279
 280 generate
 281         if (A_SIGNED) begin:BLOCK1
 282                 assign Y = |$signed(A);
 283         end else begin:BLOCK2
 284                 assign Y = |A;
 285         end
 286 endgenerate
 287
 288 endmodule
 289
 290 // --------------------------------------------------------
 291
 292 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 293 //-
 294 //-     $reduce_xor (A, B, Y)
 295 //-
 296 //- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator.
 297 //-
 298 module \$reduce_xor (A, Y);
 299
 300 parameter A_SIGNED = 0;
 301 parameter A_WIDTH = 0;
 302 parameter Y_WIDTH = 0;
 303
 304 input [A_WIDTH-1:0] A;
 305 output [Y_WIDTH-1:0] Y;
 306
 307 generate
 308         if (A_SIGNED) begin:BLOCK1
 309                 assign Y = ^$signed(A);
 310         end else begin:BLOCK2
 311                 assign Y = ^A;
 312         end
 313 endgenerate
 314
 315 endmodule
 316
 317 // --------------------------------------------------------
 318
 319 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 320 //-
 321 //-     $reduce_xnor (A, B, Y)
 322 //-
 323 //- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator.
 324 //-
 325 module \$reduce_xnor (A, Y);
 326
 327 parameter A_SIGNED = 0;
 328 parameter A_WIDTH = 0;
 329 parameter Y_WIDTH = 0;
 330
 331 input [A_WIDTH-1:0] A;
 332 output [Y_WIDTH-1:0] Y;
 333
 334 generate
 335         if (A_SIGNED) begin:BLOCK1
 336                 assign Y = ~^$signed(A);
 337         end else begin:BLOCK2
 338                 assign Y = ~^A;
 339         end
 340 endgenerate
 341
 342 endmodule
 343
 344 // --------------------------------------------------------
 345
 346 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 347 //-
 348 //-     $reduce_bool (A, B, Y)
 349 //-
 350 //- An OR reduction. This cell type is used instead of $reduce_or when a signal is
 351 //- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'.
 352 //-
 353 module \$reduce_bool (A, Y);
 354
 355 parameter A_SIGNED = 0;
 356 parameter A_WIDTH = 0;
 357 parameter Y_WIDTH = 0;
 358
 359 input [A_WIDTH-1:0] A;
 360 output [Y_WIDTH-1:0] Y;
 361
 362 generate
 363         if (A_SIGNED) begin:BLOCK1
 364                 assign Y = !(!$signed(A));
 365         end else begin:BLOCK2
 366                 assign Y = !(!A);
 367         end
 368 endgenerate
 369
 370 endmodule
 371
 372 // --------------------------------------------------------
 373
 374 module \$shl (A, B, Y);
 375
 376 parameter A_SIGNED = 0;
 377 parameter B_SIGNED = 0;
 378 parameter A_WIDTH = 0;
 379 parameter B_WIDTH = 0;
 380 parameter Y_WIDTH = 0;
 381
 382 input [A_WIDTH-1:0] A;
 383 input [B_WIDTH-1:0] B;
 384 output [Y_WIDTH-1:0] Y;
 385
 386 generate
 387         if (A_SIGNED) begin:BLOCK1
 388                 assign Y = $signed(A) << B;
 389         end else begin:BLOCK2
 390                 assign Y = A << B;
 391         end
 392 endgenerate
 393
 394 endmodule
 395
 396 // --------------------------------------------------------
 397
 398 module \$shr (A, B, Y);
 399
 400 parameter A_SIGNED = 0;
 401 parameter B_SIGNED = 0;
 402 parameter A_WIDTH = 0;
 403 parameter B_WIDTH = 0;
 404 parameter Y_WIDTH = 0;
 405
 406 input [A_WIDTH-1:0] A;
 407 input [B_WIDTH-1:0] B;
 408 output [Y_WIDTH-1:0] Y;
 409
 410 generate
 411         if (A_SIGNED) begin:BLOCK1
 412                 assign Y = $signed(A) >> B;
 413         end else begin:BLOCK2
 414                 assign Y = A >> B;
 415         end
 416 endgenerate
 417
 418 endmodule
 419
 420 // --------------------------------------------------------
 421
 422 module \$sshl (A, B, Y);
 423
 424 parameter A_SIGNED = 0;
 425 parameter B_SIGNED = 0;
 426 parameter A_WIDTH = 0;
 427 parameter B_WIDTH = 0;
 428 parameter Y_WIDTH = 0;
 429
 430 input [A_WIDTH-1:0] A;
 431 input [B_WIDTH-1:0] B;
 432 output [Y_WIDTH-1:0] Y;
 433
 434 generate
 435         if (A_SIGNED) begin:BLOCK1
 436                 assign Y = $signed(A) <<< B;
 437         end else begin:BLOCK2
 438                 assign Y = A <<< B;
 439         end
 440 endgenerate
 441
 442 endmodule
 443
 444 // --------------------------------------------------------
 445
 446 module \$sshr (A, B, Y);
 447
 448 parameter A_SIGNED = 0;
 449 parameter B_SIGNED = 0;
 450 parameter A_WIDTH = 0;
 451 parameter B_WIDTH = 0;
 452 parameter Y_WIDTH = 0;
 453
 454 input [A_WIDTH-1:0] A;
 455 input [B_WIDTH-1:0] B;
 456 output [Y_WIDTH-1:0] Y;
 457
 458 generate
 459         if (A_SIGNED) begin:BLOCK1
 460                 assign Y = $signed(A) >>> B;
 461         end else begin:BLOCK2
 462                 assign Y = A >>> B;
 463         end
 464 endgenerate
 465
 466 endmodule
 467
 468 // --------------------------------------------------------
 469
 470 module \$shift (A, B, Y);
 471
 472 parameter A_SIGNED = 0;
 473 parameter B_SIGNED = 0;
 474 parameter A_WIDTH = 0;
 475 parameter B_WIDTH = 0;
 476 parameter Y_WIDTH = 0;
 477
 478 input [A_WIDTH-1:0] A;
 479 input [B_WIDTH-1:0] B;
 480 output [Y_WIDTH-1:0] Y;
 481
 482 generate
 483         if (B_SIGNED) begin:BLOCK1
 484                 assign Y = $signed(B) < 0 ? A << -B : A >> B;
 485         end else begin:BLOCK2
 486                 assign Y = A >> B;
 487         end
 488 endgenerate
 489
 490 endmodule
 491
 492 // --------------------------------------------------------
 493
 494 module \$shiftx (A, B, Y);
 495
 496 parameter A_SIGNED = 0;
 497 parameter B_SIGNED = 0;
 498 parameter A_WIDTH = 0;
 499 parameter B_WIDTH = 0;
 500 parameter Y_WIDTH = 0;
 501
 502 input [A_WIDTH-1:0] A;
 503 input [B_WIDTH-1:0] B;
 504 output [Y_WIDTH-1:0] Y;
 505
 506 generate
 507         if (Y_WIDTH > 0)
 508                 if (B_SIGNED) begin:BLOCK1
 509                         assign Y = A[$signed(B) +: Y_WIDTH];
 510                 end else begin:BLOCK2
 511                         assign Y = A[B +: Y_WIDTH];
 512                 end
 513 endgenerate
 514
 515 endmodule
 516
 517 // --------------------------------------------------------
 518
 519 module \$fa (A, B, C, X, Y);
 520
 521 parameter WIDTH = 1;
 522
 523 input [WIDTH-1:0] A, B, C;
 524 output [WIDTH-1:0] X, Y;
 525
 526 wire [WIDTH-1:0] t1, t2, t3;
 527
 528 assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
 529 assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
 530
 531 endmodule
 532
 533 // --------------------------------------------------------
 534
 535 module \$lcu (P, G, CI, CO);
 536
 537 parameter WIDTH = 1;
 538
 539 input [WIDTH-1:0] P, G;
 540 input CI;
 541
 542 output reg [WIDTH-1:0] CO;
 543
 544 integer i;
 545 always @* begin
 546         CO = 'bx;
 547         if (^{P, G, CI} !== 1'bx) begin
 548                 CO[0] = G[0] || (P[0] && CI);
 549                 for (i = 1; i < WIDTH; i = i+1)
 550                         CO[i] = G[i] || (P[i] && CO[i-1]);
 551         end
 552 end
 553
 554 endmodule
 555
 556 // --------------------------------------------------------
 557
 558 module \$alu (A, B, CI, BI, X, Y, CO);
 559
 560 parameter A_SIGNED = 0;
 561 parameter B_SIGNED = 0;
 562 parameter A_WIDTH = 1;
 563 parameter B_WIDTH = 1;
 564 parameter Y_WIDTH = 1;
 565
 566 input [A_WIDTH-1:0] A;
 567 input [B_WIDTH-1:0] B;
 568 output [Y_WIDTH-1:0] X, Y;
 569
 570 input CI, BI;
 571 output [Y_WIDTH-1:0] CO;
 572
 573 wire [Y_WIDTH-1:0] AA, BB;
 574
 575 generate
 576         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 577                 assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
 578         end else begin:BLOCK2
 579                 assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
 580         end
 581 endgenerate
 582
 583 // this is 'x' if Y and CO should be all 'x', and '0' otherwise
 584 wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
 585
 586 assign X = AA ^ BB;
 587 assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
 588
 589 function get_carry;
 590         input a, b, c;
 591         get_carry = (a&b) | (a&c) | (b&c);
 592 endfunction
 593
 594 genvar i;
 595 generate
 596         assign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;
 597         for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3
 598                 assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;
 599         end
 600 endgenerate
 601
 602 endmodule
 603
 604 // --------------------------------------------------------
 605
 606 module \$lt (A, B, Y);
 607
 608 parameter A_SIGNED = 0;
 609 parameter B_SIGNED = 0;
 610 parameter A_WIDTH = 0;
 611 parameter B_WIDTH = 0;
 612 parameter Y_WIDTH = 0;
 613
 614 input [A_WIDTH-1:0] A;
 615 input [B_WIDTH-1:0] B;
 616 output [Y_WIDTH-1:0] Y;
 617
 618 generate
 619         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 620                 assign Y = $signed(A) < $signed(B);
 621         end else begin:BLOCK2
 622                 assign Y = A < B;
 623         end
 624 endgenerate
 625
 626 endmodule
 627
 628 // --------------------------------------------------------
 629
 630 module \$le (A, B, Y);
 631
 632 parameter A_SIGNED = 0;
 633 parameter B_SIGNED = 0;
 634 parameter A_WIDTH = 0;
 635 parameter B_WIDTH = 0;
 636 parameter Y_WIDTH = 0;
 637
 638 input [A_WIDTH-1:0] A;
 639 input [B_WIDTH-1:0] B;
 640 output [Y_WIDTH-1:0] Y;
 641
 642 generate
 643         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 644                 assign Y = $signed(A) <= $signed(B);
 645         end else begin:BLOCK2
 646                 assign Y = A <= B;
 647         end
 648 endgenerate
 649
 650 endmodule
 651
 652 // --------------------------------------------------------
 653
 654 module \$eq (A, B, Y);
 655
 656 parameter A_SIGNED = 0;
 657 parameter B_SIGNED = 0;
 658 parameter A_WIDTH = 0;
 659 parameter B_WIDTH = 0;
 660 parameter Y_WIDTH = 0;
 661
 662 input [A_WIDTH-1:0] A;
 663 input [B_WIDTH-1:0] B;
 664 output [Y_WIDTH-1:0] Y;
 665
 666 generate
 667         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 668                 assign Y = $signed(A) == $signed(B);
 669         end else begin:BLOCK2
 670                 assign Y = A == B;
 671         end
 672 endgenerate
 673
 674 endmodule
 675
 676 // --------------------------------------------------------
 677
 678 module \$ne (A, B, Y);
 679
 680 parameter A_SIGNED = 0;
 681 parameter B_SIGNED = 0;
 682 parameter A_WIDTH = 0;
 683 parameter B_WIDTH = 0;
 684 parameter Y_WIDTH = 0;
 685
 686 input [A_WIDTH-1:0] A;
 687 input [B_WIDTH-1:0] B;
 688 output [Y_WIDTH-1:0] Y;
 689
 690 generate
 691         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 692                 assign Y = $signed(A) != $signed(B);
 693         end else begin:BLOCK2
 694                 assign Y = A != B;
 695         end
 696 endgenerate
 697
 698 endmodule
 699
 700 // --------------------------------------------------------
 701
 702 module \$eqx (A, B, Y);
 703
 704 parameter A_SIGNED = 0;
 705 parameter B_SIGNED = 0;
 706 parameter A_WIDTH = 0;
 707 parameter B_WIDTH = 0;
 708 parameter Y_WIDTH = 0;
 709
 710 input [A_WIDTH-1:0] A;
 711 input [B_WIDTH-1:0] B;
 712 output [Y_WIDTH-1:0] Y;
 713
 714 generate
 715         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 716                 assign Y = $signed(A) === $signed(B);
 717         end else begin:BLOCK2
 718                 assign Y = A === B;
 719         end
 720 endgenerate
 721
 722 endmodule
 723
 724 // --------------------------------------------------------
 725
 726 module \$nex (A, B, Y);
 727
 728 parameter A_SIGNED = 0;
 729 parameter B_SIGNED = 0;
 730 parameter A_WIDTH = 0;
 731 parameter B_WIDTH = 0;
 732 parameter Y_WIDTH = 0;
 733
 734 input [A_WIDTH-1:0] A;
 735 input [B_WIDTH-1:0] B;
 736 output [Y_WIDTH-1:0] Y;
 737
 738 generate
 739         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 740                 assign Y = $signed(A) !== $signed(B);
 741         end else begin:BLOCK2
 742                 assign Y = A !== B;
 743         end
 744 endgenerate
 745
 746 endmodule
 747
 748 // --------------------------------------------------------
 749
 750 module \$ge (A, B, Y);
 751
 752 parameter A_SIGNED = 0;
 753 parameter B_SIGNED = 0;
 754 parameter A_WIDTH = 0;
 755 parameter B_WIDTH = 0;
 756 parameter Y_WIDTH = 0;
 757
 758 input [A_WIDTH-1:0] A;
 759 input [B_WIDTH-1:0] B;
 760 output [Y_WIDTH-1:0] Y;
 761
 762 generate
 763         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 764                 assign Y = $signed(A) >= $signed(B);
 765         end else begin:BLOCK2
 766                 assign Y = A >= B;
 767         end
 768 endgenerate
 769
 770 endmodule
 771
 772 // --------------------------------------------------------
 773
 774 module \$gt (A, B, Y);
 775
 776 parameter A_SIGNED = 0;
 777 parameter B_SIGNED = 0;
 778 parameter A_WIDTH = 0;
 779 parameter B_WIDTH = 0;
 780 parameter Y_WIDTH = 0;
 781
 782 input [A_WIDTH-1:0] A;
 783 input [B_WIDTH-1:0] B;
 784 output [Y_WIDTH-1:0] Y;
 785
 786 generate
 787         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 788                 assign Y = $signed(A) > $signed(B);
 789         end else begin:BLOCK2
 790                 assign Y = A > B;
 791         end
 792 endgenerate
 793
 794 endmodule
 795
 796 // --------------------------------------------------------
 797
 798 module \$add (A, B, Y);
 799
 800 parameter A_SIGNED = 0;
 801 parameter B_SIGNED = 0;
 802 parameter A_WIDTH = 0;
 803 parameter B_WIDTH = 0;
 804 parameter Y_WIDTH = 0;
 805
 806 input [A_WIDTH-1:0] A;
 807 input [B_WIDTH-1:0] B;
 808 output [Y_WIDTH-1:0] Y;
 809
 810 generate
 811         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 812                 assign Y = $signed(A) + $signed(B);
 813         end else begin:BLOCK2
 814                 assign Y = A + B;
 815         end
 816 endgenerate
 817
 818 endmodule
 819
 820 // --------------------------------------------------------
 821
 822 module \$sub (A, B, Y);
 823
 824 parameter A_SIGNED = 0;
 825 parameter B_SIGNED = 0;
 826 parameter A_WIDTH = 0;
 827 parameter B_WIDTH = 0;
 828 parameter Y_WIDTH = 0;
 829
 830 input [A_WIDTH-1:0] A;
 831 input [B_WIDTH-1:0] B;
 832 output [Y_WIDTH-1:0] Y;
 833
 834 generate
 835         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 836                 assign Y = $signed(A) - $signed(B);
 837         end else begin:BLOCK2
 838                 assign Y = A - B;
 839         end
 840 endgenerate
 841
 842 endmodule
 843
 844 // --------------------------------------------------------
 845
 846 module \$mul (A, B, Y);
 847
 848 parameter A_SIGNED = 0;
 849 parameter B_SIGNED = 0;
 850 parameter A_WIDTH = 0;
 851 parameter B_WIDTH = 0;
 852 parameter Y_WIDTH = 0;
 853
 854 input [A_WIDTH-1:0] A;
 855 input [B_WIDTH-1:0] B;
 856 output [Y_WIDTH-1:0] Y;
 857
 858 generate
 859         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 860                 assign Y = $signed(A) * $signed(B);
 861         end else begin:BLOCK2
 862                 assign Y = A * B;
 863         end
 864 endgenerate
 865
 866 endmodule
 867
 868 // --------------------------------------------------------
 869
 870 module \$macc (A, B, Y);
 871
 872 parameter A_WIDTH = 0;
 873 parameter B_WIDTH = 0;
 874 parameter Y_WIDTH = 0;
 875 parameter CONFIG = 4'b0000;
 876 parameter CONFIG_WIDTH = 4;
 877
 878 input [A_WIDTH-1:0] A;
 879 input [B_WIDTH-1:0] B;
 880 output reg [Y_WIDTH-1:0] Y;
 881
 882 // Xilinx XSIM does not like $clog2() below..
 883 function integer my_clog2;
 884         input integer v;
 885         begin
 886                 if (v > 0)
 887                         v = v - 1;
 888                 my_clog2 = 0;
 889                 while (v) begin
 890                         v = v >> 1;
 891                         my_clog2 = my_clog2 + 1;
 892                 end
 893         end
 894 endfunction
 895
 896 localparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;
 897 localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
 898 localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;
 899
 900 function [2*num_ports*num_abits-1:0] get_port_offsets;
 901         input [CONFIG_WIDTH-1:0] cfg;
 902         integer i, cursor;
 903         begin
 904                 cursor = 0;
 905                 get_port_offsets = 0;
 906                 for (i = 0; i < num_ports; i = i+1) begin
 907                         get_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;
 908                         cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];
 909                         get_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;
 910                         cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];
 911                 end
 912         end
 913 endfunction
 914
 915 localparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);
 916
 917 `define PORT_IS_SIGNED   (0 + CONFIG[4 + i*(2 + 2*num_bits)])
 918 `define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])
 919 `define PORT_SIZE_A      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])
 920 `define PORT_SIZE_B      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])
 921 `define PORT_OFFSET_A    (0 + port_offsets[2*i*num_abits +: num_abits])
 922 `define PORT_OFFSET_B    (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])
 923
 924 integer i, j;
 925 reg [Y_WIDTH-1:0] tmp_a, tmp_b;
 926
 927 always @* begin
 928         Y = 0;
 929         for (i = 0; i < num_ports; i = i+1)
 930         begin
 931                 tmp_a = 0;
 932                 tmp_b = 0;
 933
 934                 for (j = 0; j < `PORT_SIZE_A; j = j+1)
 935                         tmp_a[j] = A[`PORT_OFFSET_A + j];
 936
 937                 if (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)
 938                         for (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)
 939                                 tmp_a[j] = tmp_a[`PORT_SIZE_A-1];
 940
 941                 for (j = 0; j < `PORT_SIZE_B; j = j+1)
 942                         tmp_b[j] = A[`PORT_OFFSET_B + j];
 943
 944                 if (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)
 945                         for (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)
 946                                 tmp_b[j] = tmp_b[`PORT_SIZE_B-1];
 947
 948                 if (`PORT_SIZE_B > 0)
 949                         tmp_a = tmp_a * tmp_b;
 950
 951                 if (`PORT_DO_SUBTRACT)
 952                         Y = Y - tmp_a;
 953                 else
 954                         Y = Y + tmp_a;
 955         end
 956         for (i = 0; i < B_WIDTH; i = i+1) begin
 957                 Y = Y + B[i];
 958         end
 959 end
 960
 961 `undef PORT_IS_SIGNED
 962 `undef PORT_DO_SUBTRACT
 963 `undef PORT_SIZE_A
 964 `undef PORT_SIZE_B
 965 `undef PORT_OFFSET_A
 966 `undef PORT_OFFSET_B
 967
 968 endmodule
 969
 970 // --------------------------------------------------------
 971
 972 module \$div (A, B, Y);
 973
 974 parameter A_SIGNED = 0;
 975 parameter B_SIGNED = 0;
 976 parameter A_WIDTH = 0;
 977 parameter B_WIDTH = 0;
 978 parameter Y_WIDTH = 0;
 979
 980 input [A_WIDTH-1:0] A;
 981 input [B_WIDTH-1:0] B;
 982 output [Y_WIDTH-1:0] Y;
 983
 984 generate
 985         if (A_SIGNED && B_SIGNED) begin:BLOCK1
 986                 assign Y = $signed(A) / $signed(B);
 987         end else begin:BLOCK2
 988                 assign Y = A / B;
 989         end
 990 endgenerate
 991
 992 endmodule
 993
 994 // --------------------------------------------------------
 995
 996 module \$mod (A, B, Y);
 997
 998 parameter A_SIGNED = 0;
 999 parameter B_SIGNED = 0;
1000 parameter A_WIDTH = 0;
1001 parameter B_WIDTH = 0;
1002 parameter Y_WIDTH = 0;
1003
1004 input [A_WIDTH-1:0] A;
1005 input [B_WIDTH-1:0] B;
1006 output [Y_WIDTH-1:0] Y;
1007
1008 generate
1009         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1010                 assign Y = $signed(A) % $signed(B);
1011         end else begin:BLOCK2
1012                 assign Y = A % B;
1013         end
1014 endgenerate
1015
1016 endmodule
1017
1018 // --------------------------------------------------------
1019 `ifndef SIMLIB_NOPOW
1020
1021 module \$pow (A, B, Y);
1022
1023 parameter A_SIGNED = 0;
1024 parameter B_SIGNED = 0;
1025 parameter A_WIDTH = 0;
1026 parameter B_WIDTH = 0;
1027 parameter Y_WIDTH = 0;
1028
1029 input [A_WIDTH-1:0] A;
1030 input [B_WIDTH-1:0] B;
1031 output [Y_WIDTH-1:0] Y;
1032
1033 generate
1034         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1035                 assign Y = $signed(A) ** $signed(B);
1036         end else if (A_SIGNED) begin:BLOCK2
1037                 assign Y = $signed(A) ** B;
1038         end else if (B_SIGNED) begin:BLOCK3
1039                 assign Y = A ** $signed(B);
1040         end else begin:BLOCK4
1041                 assign Y = A ** B;
1042         end
1043 endgenerate
1044
1045 endmodule
1046
1047 `endif
1048 // --------------------------------------------------------
1049
1050 module \$logic_not (A, Y);
1051
1052 parameter A_SIGNED = 0;
1053 parameter A_WIDTH = 0;
1054 parameter Y_WIDTH = 0;
1055
1056 input [A_WIDTH-1:0] A;
1057 output [Y_WIDTH-1:0] Y;
1058
1059 generate
1060         if (A_SIGNED) begin:BLOCK1
1061                 assign Y = !$signed(A);
1062         end else begin:BLOCK2
1063                 assign Y = !A;
1064         end
1065 endgenerate
1066
1067 endmodule
1068
1069 // --------------------------------------------------------
1070
1071 module \$logic_and (A, B, Y);
1072
1073 parameter A_SIGNED = 0;
1074 parameter B_SIGNED = 0;
1075 parameter A_WIDTH = 0;
1076 parameter B_WIDTH = 0;
1077 parameter Y_WIDTH = 0;
1078
1079 input [A_WIDTH-1:0] A;
1080 input [B_WIDTH-1:0] B;
1081 output [Y_WIDTH-1:0] Y;
1082
1083 generate
1084         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1085                 assign Y = $signed(A) && $signed(B);
1086         end else begin:BLOCK2
1087                 assign Y = A && B;
1088         end
1089 endgenerate
1090
1091 endmodule
1092
1093 // --------------------------------------------------------
1094
1095 module \$logic_or (A, B, Y);
1096
1097 parameter A_SIGNED = 0;
1098 parameter B_SIGNED = 0;
1099 parameter A_WIDTH = 0;
1100 parameter B_WIDTH = 0;
1101 parameter Y_WIDTH = 0;
1102
1103 input [A_WIDTH-1:0] A;
1104 input [B_WIDTH-1:0] B;
1105 output [Y_WIDTH-1:0] Y;
1106
1107 generate
1108         if (A_SIGNED && B_SIGNED) begin:BLOCK1
1109                 assign Y = $signed(A) || $signed(B);
1110         end else begin:BLOCK2
1111                 assign Y = A || B;
1112         end
1113 endgenerate
1114
1115 endmodule
1116
1117 // --------------------------------------------------------
1118
1119 module \$slice (A, Y);
1120
1121 parameter OFFSET = 0;
1122 parameter A_WIDTH = 0;
1123 parameter Y_WIDTH = 0;
1124
1125 input [A_WIDTH-1:0] A;
1126 output [Y_WIDTH-1:0] Y;
1127
1128 assign Y = A >> OFFSET;
1129
1130 endmodule
1131
1132 // --------------------------------------------------------
1133
1134 module \$concat (A, B, Y);
1135
1136 parameter A_WIDTH = 0;
1137 parameter B_WIDTH = 0;
1138
1139 input [A_WIDTH-1:0] A;
1140 input [B_WIDTH-1:0] B;
1141 output [A_WIDTH+B_WIDTH-1:0] Y;
1142
1143 assign Y = {B, A};
1144
1145 endmodule
1146
1147 // --------------------------------------------------------
1148
1149 module \$mux (A, B, S, Y);
1150
1151 parameter WIDTH = 0;
1152
1153 input [WIDTH-1:0] A, B;
1154 input S;
1155 output reg [WIDTH-1:0] Y;
1156
1157 always @* begin
1158         if (S)
1159                 Y = B;
1160         else
1161                 Y = A;
1162 end
1163
1164 endmodule
1165
1166 // --------------------------------------------------------
1167
1168 module \$pmux (A, B, S, Y);
1169
1170 parameter WIDTH = 0;
1171 parameter S_WIDTH = 0;
1172
1173 input [WIDTH-1:0] A;
1174 input [WIDTH*S_WIDTH-1:0] B;
1175 input [S_WIDTH-1:0] S;
1176 output reg [WIDTH-1:0] Y;
1177
1178 integer i;
1179 reg found_active_sel_bit;
1180
1181 always @* begin
1182         Y = A;
1183         found_active_sel_bit = 0;
1184         for (i = 0; i < S_WIDTH; i = i+1)
1185                 if (S[i]) begin
1186                         Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i);
1187                         found_active_sel_bit = 1;
1188                 end
1189 end
1190
1191 endmodule
1192
1193 // --------------------------------------------------------
1194 `ifndef SIMLIB_NOLUT
1195
1196 module \$lut (A, Y);
1197
1198 parameter WIDTH = 0;
1199 parameter LUT = 0;
1200
1201 input [WIDTH-1:0] A;
1202 output reg Y;
1203
1204 wire lut0_out, lut1_out;
1205
1206 generate
1207         if (WIDTH <= 1) begin:simple
1208                 assign {lut1_out, lut0_out} = LUT;
1209         end else begin:complex
1210                 \$lut #( .WIDTH(WIDTH-1), .LUT(LUT                  ) ) lut0 ( .A(A[WIDTH-2:0]), .Y(lut0_out) );
1211                 \$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .A(A[WIDTH-2:0]), .Y(lut1_out) );
1212         end
1213
1214         if (WIDTH > 0) begin:lutlogic
1215                 always @* begin
1216                         casez ({A[WIDTH-1], lut0_out, lut1_out})
1217                                 3'b?11: Y = 1'b1;
1218                                 3'b?00: Y = 1'b0;
1219                                 3'b0??: Y = lut0_out;
1220                                 3'b1??: Y = lut1_out;
1221                                 default: Y = 1'bx;
1222                         endcase
1223                 end
1224         end
1225 endgenerate
1226
1227 endmodule
1228
1229 `endif
1230 // --------------------------------------------------------
1231
1232 module \$sop (A, Y);
1233
1234 parameter WIDTH = 0;
1235 parameter DEPTH = 0;
1236 parameter TABLE = 0;
1237
1238 input [WIDTH-1:0] A;
1239 output reg Y;
1240
1241 integer i, j;
1242 reg match;
1243
1244 always @* begin
1245         Y = 0;
1246         for (i = 0; i < DEPTH; i=i+1) begin
1247                 match = 1;
1248                 for (j = 0; j < WIDTH; j=j+1) begin
1249                         if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
1250                         if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
1251                 end
1252                 if (match) Y = 1;
1253         end
1254 end
1255
1256 endmodule
1257
1258 // --------------------------------------------------------
1259
1260 module \$tribuf (A, EN, Y);
1261
1262 parameter WIDTH = 0;
1263
1264 input [WIDTH-1:0] A;
1265 input EN;
1266 output [WIDTH-1:0] Y;
1267
1268 assign Y = EN ? A : 'bz;
1269
1270 endmodule
1271
1272 // --------------------------------------------------------
1273
1274 module \$specify2 (EN, SRC, DST);
1275
1276 parameter FULL = 0;
1277 parameter SRC_WIDTH = 1;
1278 parameter DST_WIDTH = 1;
1279
1280 parameter SRC_DST_PEN = 0;
1281 parameter SRC_DST_POL = 0;
1282
1283 parameter T_RISE_MIN = 0;
1284 parameter T_RISE_TYP = 0;
1285 parameter T_RISE_MAX = 0;
1286
1287 parameter T_FALL_MIN = 0;
1288 parameter T_FALL_TYP = 0;
1289 parameter T_FALL_MAX = 0;
1290
1291 input EN;
1292 input [SRC_WIDTH-1:0] SRC;
1293 input [DST_WIDTH-1:0] DST;
1294
1295 localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
1296
1297 `ifdef SIMLIB_SPECIFY
1298 specify
1299         if (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1300         if (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1301         if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1302         if (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1303         if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1304         if (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1305 endspecify
1306 `endif
1307
1308 endmodule
1309
1310 // --------------------------------------------------------
1311
1312 module \$specify3 (EN, SRC, DST, DAT);
1313
1314 parameter FULL = 0;
1315 parameter SRC_WIDTH = 1;
1316 parameter DST_WIDTH = 1;
1317
1318 parameter EDGE_EN = 0;
1319 parameter EDGE_POL = 0;
1320
1321 parameter SRC_DST_PEN = 0;
1322 parameter SRC_DST_POL = 0;
1323
1324 parameter DAT_DST_PEN = 0;
1325 parameter DAT_DST_POL = 0;
1326
1327 parameter T_RISE_MIN = 0;
1328 parameter T_RISE_TYP = 0;
1329 parameter T_RISE_MAX = 0;
1330
1331 parameter T_FALL_MIN = 0;
1332 parameter T_FALL_TYP = 0;
1333 parameter T_FALL_MAX = 0;
1334
1335 input EN;
1336 input [SRC_WIDTH-1:0] SRC;
1337 input [DST_WIDTH-1:0] DST, DAT;
1338
1339 localparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;
1340 localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
1341 localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
1342
1343 `ifdef SIMLIB_SPECIFY
1344 specify
1345         // DD=0
1346
1347         if (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1348         if (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1349         if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1350         if (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1351         if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1352         if (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1353
1354         if (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1355         if (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1356         if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1357         if (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1358         if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1359         if (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1360
1361         if (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1362         if (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1363         if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1364         if (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1365         if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1366         if (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1367
1368         // DD=1
1369
1370         if (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1371         if (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1372         if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1373         if (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1374         if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1375         if (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1376
1377         if (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1378         if (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1379         if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1380         if (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1381         if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1382         if (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1383
1384         if (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1385         if (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1386         if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1387         if (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1388         if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1389         if (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1390
1391         // DD=2
1392
1393         if (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1394         if (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1395         if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1396         if (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1397         if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1398         if (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1399
1400         if (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1401         if (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1402         if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1403         if (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1404         if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1405         if (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1406
1407         if (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1408         if (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1409         if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1410         if (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1411         if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1412         if (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
1413 endspecify
1414 `endif
1415
1416 endmodule
1417
1418 // --------------------------------------------------------
1419
1420 module \$specrule (EN_SRC, EN_DST, SRC, DST);
1421
1422 parameter TYPE = "";
1423 parameter T_LIMIT = 0;
1424 parameter T_LIMIT2 = 0;
1425
1426 parameter SRC_WIDTH = 1;
1427 parameter DST_WIDTH = 1;
1428
1429 parameter SRC_PEN = 0;
1430 parameter SRC_POL = 0;
1431
1432 parameter DST_PEN = 0;
1433 parameter DST_POL = 0;
1434
1435 input EN_SRC, EN_DST;
1436 input [SRC_WIDTH-1:0] SRC;
1437 input [DST_WIDTH-1:0] DST;
1438
1439 `ifdef SIMLIB_SPECIFY
1440 specify
1441         // TBD
1442 endspecify
1443 `endif
1444
1445 endmodule
1446
1447 // --------------------------------------------------------
1448
1449 module \$assert (A, EN);
1450
1451 input A, EN;
1452
1453 `ifndef SIMLIB_NOCHECKS
1454 always @* begin
1455         if (A !== 1'b1 && EN === 1'b1) begin
1456                 $display("Assertion %m failed!");
1457                 $stop;
1458         end
1459 end
1460 `endif
1461
1462 endmodule
1463
1464 // --------------------------------------------------------
1465
1466 module \$assume (A, EN);
1467
1468 input A, EN;
1469
1470 `ifndef SIMLIB_NOCHECKS
1471 always @* begin
1472         if (A !== 1'b1 && EN === 1'b1) begin
1473                 $display("Assumption %m failed!");
1474                 $stop;
1475         end
1476 end
1477 `endif
1478
1479 endmodule
1480
1481 // --------------------------------------------------------
1482
1483 module \$live (A, EN);
1484
1485 input A, EN;
1486
1487 endmodule
1488
1489 // --------------------------------------------------------
1490
1491 module \$fair (A, EN);
1492
1493 input A, EN;
1494
1495 endmodule
1496
1497 // --------------------------------------------------------
1498
1499 module \$cover (A, EN);
1500
1501 input A, EN;
1502
1503 endmodule
1504
1505 // --------------------------------------------------------
1506
1507 module \$initstate (Y);
1508
1509 output reg Y = 1;
1510 reg [3:0] cnt = 1;
1511 reg trig = 0;
1512
1513 initial trig <= 1;
1514
1515 always @(cnt, trig) begin
1516         Y <= |cnt;
1517         cnt <= cnt + |cnt;
1518 end
1519
1520 endmodule
1521
1522 // --------------------------------------------------------
1523
1524 module \$anyconst (Y);
1525
1526 parameter WIDTH = 0;
1527
1528 output [WIDTH-1:0] Y;
1529
1530 assign Y = 'bx;
1531
1532 endmodule
1533
1534 // --------------------------------------------------------
1535
1536 module \$anyseq (Y);
1537
1538 parameter WIDTH = 0;
1539
1540 output [WIDTH-1:0] Y;
1541
1542 assign Y = 'bx;
1543
1544 endmodule
1545
1546 // --------------------------------------------------------
1547
1548 module \$allconst (Y);
1549
1550 parameter WIDTH = 0;
1551
1552 output [WIDTH-1:0] Y;
1553
1554 assign Y = 'bx;
1555
1556 endmodule
1557
1558 // --------------------------------------------------------
1559
1560 module \$allseq (Y);
1561
1562 parameter WIDTH = 0;
1563
1564 output [WIDTH-1:0] Y;
1565
1566 assign Y = 'bx;
1567
1568 endmodule
1569
1570 // --------------------------------------------------------
1571
1572 module \$equiv (A, B, Y);
1573
1574 input A, B;
1575 output Y;
1576
1577 assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
1578
1579 `ifndef SIMLIB_NOCHECKS
1580 always @* begin
1581         if (A !== 1'bx && A !== B) begin
1582                 $display("Equivalence failed!");
1583                 $stop;
1584         end
1585 end
1586 `endif
1587
1588 endmodule
1589
1590 // --------------------------------------------------------
1591 `ifndef SIMLIB_NOSR
1592
1593 module \$sr (SET, CLR, Q);
1594
1595 parameter WIDTH = 0;
1596 parameter SET_POLARITY = 1'b1;
1597 parameter CLR_POLARITY = 1'b1;
1598
1599 input [WIDTH-1:0] SET, CLR;
1600 output reg [WIDTH-1:0] Q;
1601
1602 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
1603 wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
1604
1605 genvar i;
1606 generate
1607         for (i = 0; i < WIDTH; i = i+1) begin:bitslices
1608                 always @(posedge pos_set[i], posedge pos_clr[i])
1609                         if (pos_clr[i])
1610                                 Q[i] <= 0;
1611                         else if (pos_set[i])
1612                                 Q[i] <= 1;
1613         end
1614 endgenerate
1615
1616 endmodule
1617
1618 `endif
1619 // --------------------------------------------------------
1620 `ifdef SIMLIB_FF
1621
1622 module \$ff (D, Q);
1623
1624 parameter WIDTH = 0;
1625
1626 input [WIDTH-1:0] D;
1627 output reg [WIDTH-1:0] Q;
1628
1629 always @($global_clk) begin
1630         Q <= D;
1631 end
1632
1633 endmodule
1634
1635 `endif
1636 // --------------------------------------------------------
1637
1638 module \$dff (CLK, D, Q);
1639
1640 parameter WIDTH = 0;
1641 parameter CLK_POLARITY = 1'b1;
1642
1643 input CLK;
1644 input [WIDTH-1:0] D;
1645 output reg [WIDTH-1:0] Q;
1646 wire pos_clk = CLK == CLK_POLARITY;
1647
1648 always @(posedge pos_clk) begin
1649         Q <= D;
1650 end
1651
1652 endmodule
1653
1654 // --------------------------------------------------------
1655
1656 module \$dffe (CLK, EN, D, Q);
1657
1658 parameter WIDTH = 0;
1659 parameter CLK_POLARITY = 1'b1;
1660 parameter EN_POLARITY = 1'b1;
1661
1662 input CLK, EN;
1663 input [WIDTH-1:0] D;
1664 output reg [WIDTH-1:0] Q;
1665 wire pos_clk = CLK == CLK_POLARITY;
1666
1667 always @(posedge pos_clk) begin
1668         if (EN == EN_POLARITY) Q <= D;
1669 end
1670
1671 endmodule
1672
1673 // --------------------------------------------------------
1674 `ifndef SIMLIB_NOSR
1675
1676 module \$dffsr (CLK, SET, CLR, D, Q);
1677
1678 parameter WIDTH = 0;
1679 parameter CLK_POLARITY = 1'b1;
1680 parameter SET_POLARITY = 1'b1;
1681 parameter CLR_POLARITY = 1'b1;
1682
1683 input CLK;
1684 input [WIDTH-1:0] SET, CLR, D;
1685 output reg [WIDTH-1:0] Q;
1686
1687 wire pos_clk = CLK == CLK_POLARITY;
1688 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
1689 wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
1690
1691 genvar i;
1692 generate
1693         for (i = 0; i < WIDTH; i = i+1) begin:bitslices
1694                 always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
1695                         if (pos_clr[i])
1696                                 Q[i] <= 0;
1697                         else if (pos_set[i])
1698                                 Q[i] <= 1;
1699                         else
1700                                 Q[i] <= D[i];
1701         end
1702 endgenerate
1703
1704 endmodule
1705
1706 `endif
1707 // --------------------------------------------------------
1708
1709 module \$adff (CLK, ARST, D, Q);
1710
1711 parameter WIDTH = 0;
1712 parameter CLK_POLARITY = 1'b1;
1713 parameter ARST_POLARITY = 1'b1;
1714 parameter ARST_VALUE = 0;
1715
1716 input CLK, ARST;
1717 input [WIDTH-1:0] D;
1718 output reg [WIDTH-1:0] Q;
1719 wire pos_clk = CLK == CLK_POLARITY;
1720 wire pos_arst = ARST == ARST_POLARITY;
1721
1722 always @(posedge pos_clk, posedge pos_arst) begin
1723         if (pos_arst)
1724                 Q <= ARST_VALUE;
1725         else
1726                 Q <= D;
1727 end
1728
1729 endmodule
1730
1731 // --------------------------------------------------------
1732
1733 module \$dlatch (EN, D, Q);
1734
1735 parameter WIDTH = 0;
1736 parameter EN_POLARITY = 1'b1;
1737
1738 input EN;
1739 input [WIDTH-1:0] D;
1740 output reg [WIDTH-1:0] Q;
1741
1742 always @* begin
1743         if (EN == EN_POLARITY)
1744                 Q = D;
1745 end
1746
1747 endmodule
1748
1749 // --------------------------------------------------------
1750 `ifndef SIMLIB_NOSR
1751
1752 module \$dlatchsr (EN, SET, CLR, D, Q);
1753
1754 parameter WIDTH = 0;
1755 parameter EN_POLARITY = 1'b1;
1756 parameter SET_POLARITY = 1'b1;
1757 parameter CLR_POLARITY = 1'b1;
1758
1759 input EN;
1760 input [WIDTH-1:0] SET, CLR, D;
1761 output reg [WIDTH-1:0] Q;
1762
1763 wire pos_en = EN == EN_POLARITY;
1764 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
1765 wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
1766
1767 genvar i;
1768 generate
1769         for (i = 0; i < WIDTH; i = i+1) begin:bitslices
1770                 always @*
1771                         if (pos_clr[i])
1772                                 Q[i] = 0;
1773                         else if (pos_set[i])
1774                                 Q[i] = 1;
1775                         else if (pos_en)
1776                                 Q[i] = D[i];
1777         end
1778 endgenerate
1779
1780 endmodule
1781
1782 `endif
1783 // --------------------------------------------------------
1784
1785 module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
1786
1787 parameter NAME = "";
1788
1789 parameter CLK_POLARITY = 1'b1;
1790 parameter ARST_POLARITY = 1'b1;
1791
1792 parameter CTRL_IN_WIDTH = 1;
1793 parameter CTRL_OUT_WIDTH = 1;
1794
1795 parameter STATE_BITS = 1;
1796 parameter STATE_NUM = 1;
1797 parameter STATE_NUM_LOG2 = 1;
1798 parameter STATE_RST = 0;
1799 parameter STATE_TABLE = 1'b0;
1800
1801 parameter TRANS_NUM = 1;
1802 parameter TRANS_TABLE = 4'b0x0x;
1803
1804 input CLK, ARST;
1805 input [CTRL_IN_WIDTH-1:0] CTRL_IN;
1806 output reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;
1807
1808 wire pos_clk = CLK == CLK_POLARITY;
1809 wire pos_arst = ARST == ARST_POLARITY;
1810
1811 reg [STATE_BITS-1:0] state;
1812 reg [STATE_BITS-1:0] state_tmp;
1813 reg [STATE_BITS-1:0] next_state;
1814
1815 reg [STATE_BITS-1:0] tr_state_in;
1816 reg [STATE_BITS-1:0] tr_state_out;
1817 reg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;
1818 reg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;
1819
1820 integer i;
1821
1822 task tr_fetch;
1823         input [31:0] tr_num;
1824         reg [31:0] tr_pos;
1825         reg [STATE_NUM_LOG2-1:0] state_num;
1826         begin
1827                 tr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;
1828                 tr_ctrl_out = TRANS_TABLE >> tr_pos;
1829                 tr_pos = tr_pos + CTRL_OUT_WIDTH;
1830                 state_num = TRANS_TABLE >> tr_pos;
1831                 tr_state_out = STATE_TABLE >> (STATE_BITS*state_num);
1832                 tr_pos = tr_pos + STATE_NUM_LOG2;
1833                 tr_ctrl_in = TRANS_TABLE >> tr_pos;
1834                 tr_pos = tr_pos + CTRL_IN_WIDTH;
1835                 state_num = TRANS_TABLE >> tr_pos;
1836                 tr_state_in = STATE_TABLE >> (STATE_BITS*state_num);
1837                 tr_pos = tr_pos + STATE_NUM_LOG2;
1838         end
1839 endtask
1840
1841 always @(posedge pos_clk, posedge pos_arst) begin
1842         if (pos_arst) begin
1843                 state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
1844                 for (i = 0; i < STATE_BITS; i = i+1)
1845                         if (state_tmp[i] === 1'bz)
1846                                 state_tmp[i] = 0;
1847                 state <= state_tmp;
1848         end else begin
1849                 state_tmp = next_state;
1850                 for (i = 0; i < STATE_BITS; i = i+1)
1851                         if (state_tmp[i] === 1'bz)
1852                                 state_tmp[i] = 0;
1853                 state <= state_tmp;
1854         end
1855 end
1856
1857 always @(state, CTRL_IN) begin
1858         next_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
1859         CTRL_OUT <= 'bx;
1860         // $display("---");
1861         // $display("Q: %b %b", state, CTRL_IN);
1862         for (i = 0; i < TRANS_NUM; i = i+1) begin
1863                 tr_fetch(i);
1864                 // $display("T: %b %b -> %b %b [%d]", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);
1865                 casez ({state, CTRL_IN})
1866                         {tr_state_in, tr_ctrl_in}: begin
1867                                 // $display("-> %b %b <-   MATCH", state, CTRL_IN);
1868                                 {next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};
1869                         end
1870                 endcase
1871         end
1872 end
1873
1874 endmodule
1875
1876 // --------------------------------------------------------
1877 `ifndef SIMLIB_NOMEM
1878
1879 module \$memrd (CLK, EN, ADDR, DATA);
1880
1881 parameter MEMID = "";
1882 parameter ABITS = 8;
1883 parameter WIDTH = 8;
1884
1885 parameter CLK_ENABLE = 0;
1886 parameter CLK_POLARITY = 0;
1887 parameter TRANSPARENT = 0;
1888
1889 input CLK, EN;
1890 input [ABITS-1:0] ADDR;
1891 output [WIDTH-1:0] DATA;
1892
1893 initial begin
1894         if (MEMID != "") begin
1895                 $display("ERROR: Found non-simulatable instance of $memrd!");
1896                 $finish;
1897         end
1898 end
1899
1900 endmodule
1901
1902 // --------------------------------------------------------
1903
1904 module \$memwr (CLK, EN, ADDR, DATA);
1905
1906 parameter MEMID = "";
1907 parameter ABITS = 8;
1908 parameter WIDTH = 8;
1909
1910 parameter CLK_ENABLE = 0;
1911 parameter CLK_POLARITY = 0;
1912 parameter PRIORITY = 0;
1913
1914 input CLK;
1915 input [WIDTH-1:0] EN;
1916 input [ABITS-1:0] ADDR;
1917 input [WIDTH-1:0] DATA;
1918
1919 initial begin
1920         if (MEMID != "") begin
1921                 $display("ERROR: Found non-simulatable instance of $memwr!");
1922                 $finish;
1923         end
1924 end
1925
1926 endmodule
1927
1928 // --------------------------------------------------------
1929
1930 module \$meminit (ADDR, DATA);
1931
1932 parameter MEMID = "";
1933 parameter ABITS = 8;
1934 parameter WIDTH = 8;
1935 parameter WORDS = 1;
1936
1937 parameter PRIORITY = 0;
1938
1939 input [ABITS-1:0] ADDR;
1940 input [WORDS*WIDTH-1:0] DATA;
1941
1942 initial begin
1943         if (MEMID != "") begin
1944                 $display("ERROR: Found non-simulatable instance of $meminit!");
1945                 $finish;
1946         end
1947 end
1948
1949 endmodule
1950
1951 // --------------------------------------------------------
1952
1953 module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
1954
1955 parameter MEMID = "";
1956 parameter signed SIZE = 4;
1957 parameter signed OFFSET = 0;
1958 parameter signed ABITS = 2;
1959 parameter signed WIDTH = 8;
1960 parameter signed INIT = 1'bx;
1961
1962 parameter signed RD_PORTS = 1;
1963 parameter RD_CLK_ENABLE = 1'b1;
1964 parameter RD_CLK_POLARITY = 1'b1;
1965 parameter RD_TRANSPARENT = 1'b1;
1966
1967 parameter signed WR_PORTS = 1;
1968 parameter WR_CLK_ENABLE = 1'b1;
1969 parameter WR_CLK_POLARITY = 1'b1;
1970
1971 input [RD_PORTS-1:0] RD_CLK;
1972 input [RD_PORTS-1:0] RD_EN;
1973 input [RD_PORTS*ABITS-1:0] RD_ADDR;
1974 output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
1975
1976 input [WR_PORTS-1:0] WR_CLK;
1977 input [WR_PORTS*WIDTH-1:0] WR_EN;
1978 input [WR_PORTS*ABITS-1:0] WR_ADDR;
1979 input [WR_PORTS*WIDTH-1:0] WR_DATA;
1980
1981 reg [WIDTH-1:0] memory [SIZE-1:0];
1982
1983 integer i, j;
1984 reg [WR_PORTS-1:0] LAST_WR_CLK;
1985 reg [RD_PORTS-1:0] LAST_RD_CLK;
1986
1987 function port_active;
1988         input clk_enable;
1989         input clk_polarity;
1990         input last_clk;
1991         input this_clk;
1992         begin
1993                 casez ({clk_enable, clk_polarity, last_clk, this_clk})
1994                         4'b0???: port_active = 1;
1995                         4'b1101: port_active = 1;
1996                         4'b1010: port_active = 1;
1997                         default: port_active = 0;
1998                 endcase
1999         end
2000 endfunction
2001
2002 initial begin
2003         for (i = 0; i < SIZE; i = i+1)
2004                 memory[i] = INIT >>> (i*WIDTH);
2005 end
2006
2007 always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
2008 `ifdef SIMLIB_MEMDELAY
2009         #`SIMLIB_MEMDELAY;
2010 `endif
2011         for (i = 0; i < RD_PORTS; i = i+1) begin
2012                 if (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
2013                         // $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
2014                         RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
2015                 end
2016         end
2017
2018         for (i = 0; i < WR_PORTS; i = i+1) begin
2019                 if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
2020                         for (j = 0; j < WIDTH; j = j+1)
2021                                 if (WR_EN[i*WIDTH+j]) begin
2022                                         // $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
2023                                         memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
2024                                 end
2025         end
2026
2027         for (i = 0; i < RD_PORTS; i = i+1) begin
2028                 if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
2029                         // $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
2030                         RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
2031                 end
2032         end
2033
2034         LAST_RD_CLK <= RD_CLK;
2035         LAST_WR_CLK <= WR_CLK;
2036 end
2037
2038 endmodule
2039
2040 `endif
2041
2042 // --------------------------------------------------------