2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthPass
: public ScriptPass
30 SynthPass() : ScriptPass("synth", "generic synthesis script") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth [options]\n");
38 log("This command runs the default synthesis script. This command does not operate\n");
39 log("on partly selected designs.\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module (default='top')\n");
45 log(" automatically determine the top of the design hierarchy\n");
48 log(" flatten the design before synthesis. this will pass '-auto-top' to\n");
49 log(" 'hierarchy' if no top module is specified.\n");
51 log(" -encfile <file>\n");
52 log(" passed to 'fsm_recode' via 'fsm'\n");
55 log(" perform synthesis for a k-LUT architecture.\n");
58 log(" do not run FSM optimization\n");
61 log(" do not run abc (as if yosys was compiled without ABC support)\n");
64 log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
65 log(" their direct form ($add, $sub, etc.).\n");
68 log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
71 log(" do not run SAT-based resource sharing\n");
73 log(" -run <from_label>[:<to_label>]\n");
74 log(" only run the commands between the labels (see below). an empty\n");
75 log(" from label is synonymous to 'begin', and empty to label is\n");
76 log(" synonymous to the end of the command list.\n");
79 log(" use new ABC9 flow (EXPERIMENTAL)\n");
82 log(" use FlowMap LUT techmapping instead of ABC\n");
85 log("The following commands are executed by this synthesis command:\n");
90 string top_module
, fsm_opts
, memory_opts
, abc
;
91 bool autotop
, flatten
, noalumacc
, nofsm
, noabc
, noshare
, flowmap
;
94 void clear_flags() YS_OVERRIDE
111 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
113 string run_from
, run_to
;
117 for (argidx
= 1; argidx
< args
.size(); argidx
++)
119 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
120 top_module
= args
[++argidx
];
123 if (args
[argidx
] == "-encfile" && argidx
+1 < args
.size()) {
124 fsm_opts
= " -encfile " + args
[++argidx
];
127 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
128 size_t pos
= args
[argidx
+1].find(':');
129 if (pos
== std::string::npos
) {
130 run_from
= args
[++argidx
];
131 run_to
= args
[argidx
];
133 run_from
= args
[++argidx
].substr(0, pos
);
134 run_to
= args
[argidx
].substr(pos
+1);
138 if (args
[argidx
] == "-auto-top") {
142 if (args
[argidx
] == "-flatten") {
146 if (args
[argidx
] == "-lut") {
147 lut
= atoi(args
[++argidx
].c_str());
150 if (args
[argidx
] == "-nofsm") {
154 if (args
[argidx
] == "-noabc") {
158 if (args
[argidx
] == "-noalumacc") {
162 if (args
[argidx
] == "-nordff") {
163 memory_opts
+= " -nordff";
166 if (args
[argidx
] == "-noshare") {
170 if (args
[argidx
] == "-abc9") {
174 if (args
[argidx
] == "-flowmap") {
180 extra_args(args
, argidx
, design
);
182 if (!design
->full_selection())
183 log_cmd_error("This command only operates on fully selected designs!\n");
185 if (abc
== "abc9" && !lut
)
186 log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
188 log_cmd_error("FlowMap is only supported for FPGA synthesis (using '-lut' option)\n");
190 log_header(design
, "Executing SYNTH pass.\n");
193 run_script(design
, run_from
, run_to
);
198 void script() YS_OVERRIDE
200 if (check_label("begin"))
203 run("hierarchy -check [-top <top> | -auto-top]");
205 if (top_module
.empty()) {
206 if (flatten
|| autotop
)
207 run("hierarchy -check -auto-top");
209 run("hierarchy -check");
211 run(stringf("hierarchy -check -top %s", top_module
.c_str()));
215 if (check_label("coarse"))
218 if (help_mode
|| flatten
)
219 run("flatten", " (if -flatten)");
228 run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
230 run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut
));
232 run("alumacc", " (unless -noalumacc)");
234 run("share", " (unless -noshare)");
237 run("fsm" + fsm_opts
, " (unless -nofsm)");
239 run("memory -nomap" + memory_opts
);
243 if (check_label("fine"))
245 run("opt -fast -full");
251 run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
252 run("clean; opt_lut", " (if -noabc and -lut)");
253 run("flowmap -maxlut K", " (if -flowmap and -lut)");
255 else if (noabc
&& lut
)
257 run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut
));
258 run("clean; opt_lut");
262 run(stringf("flowmap -maxlut %d", lut
));
266 if (!noabc
&& !flowmap
) {
267 #ifdef YOSYS_ENABLE_ABC
270 run(abc
+ " -fast", " (unless -noabc, unless -lut)");
271 run(abc
+ " -fast -lut k", "(unless -noabc, if -lut)");
276 run(stringf("%s -fast -lut %d", abc
.c_str(), lut
));
280 run("opt -fast", " (unless -noabc)");
285 if (check_label("check"))
287 run("hierarchy -check");
294 PRIVATE_NAMESPACE_END