techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  43 module simplemap_bool_ops;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  48 module simplemap_reduce_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  53 module simplemap_logic_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$pos $slice $concat $mux" *)
  58 module simplemap_various;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  63 module simplemap_registers;
  64 endmodule
  65
  66
  67 // --------------------------------------------------------
  68 // Trivial substitutions
  69 // --------------------------------------------------------
  70
  71 module \$neg (A, Y);
  72         parameter A_SIGNED = 0;
  73         parameter A_WIDTH = 1;
  74         parameter Y_WIDTH = 1;
  75
  76         input [A_WIDTH-1:0] A;
  77         output [Y_WIDTH-1:0] Y;
  78
  79         \$sub #(
  80                 .A_SIGNED(A_SIGNED),
  81                 .B_SIGNED(A_SIGNED),
  82                 .A_WIDTH(1),
  83                 .B_WIDTH(A_WIDTH),
  84                 .Y_WIDTH(Y_WIDTH)
  85         ) _TECHMAP_REPLACE_ (
  86                 .A(1'b0),
  87                 .B(A),
  88                 .Y(Y)
  89         );
  90 endmodule
  91
  92 module \$ge (A, B, Y);
  93         parameter A_SIGNED = 0;
  94         parameter B_SIGNED = 0;
  95         parameter A_WIDTH = 1;
  96         parameter B_WIDTH = 1;
  97         parameter Y_WIDTH = 1;
  98
  99         input [A_WIDTH-1:0] A;
 100         input [B_WIDTH-1:0] B;
 101         output [Y_WIDTH-1:0] Y;
 102
 103         \$le #(
 104                 .A_SIGNED(B_SIGNED),
 105                 .B_SIGNED(A_SIGNED),
 106                 .A_WIDTH(B_WIDTH),
 107                 .B_WIDTH(A_WIDTH),
 108                 .Y_WIDTH(Y_WIDTH)
 109         ) _TECHMAP_REPLACE_ (
 110                 .A(B),
 111                 .B(A),
 112                 .Y(Y)
 113         );
 114 endmodule
 115
 116 module \$gt (A, B, Y);
 117         parameter A_SIGNED = 0;
 118         parameter B_SIGNED = 0;
 119         parameter A_WIDTH = 1;
 120         parameter B_WIDTH = 1;
 121         parameter Y_WIDTH = 1;
 122
 123         input [A_WIDTH-1:0] A;
 124         input [B_WIDTH-1:0] B;
 125         output [Y_WIDTH-1:0] Y;
 126
 127         \$lt #(
 128                 .A_SIGNED(B_SIGNED),
 129                 .B_SIGNED(A_SIGNED),
 130                 .A_WIDTH(B_WIDTH),
 131                 .B_WIDTH(A_WIDTH),
 132                 .Y_WIDTH(Y_WIDTH)
 133         ) _TECHMAP_REPLACE_ (
 134                 .A(B),
 135                 .B(A),
 136                 .Y(Y)
 137         );
 138 endmodule
 139
 140
 141 // --------------------------------------------------------
 142 // Shift operators
 143 // --------------------------------------------------------
 144
 145 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 146 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 147         parameter A_SIGNED = 0;
 148         parameter B_SIGNED = 0;
 149         parameter A_WIDTH = 1;
 150         parameter B_WIDTH = 1;
 151         parameter Y_WIDTH = 1;
 152
 153         parameter _TECHMAP_CELLTYPE_ = "";
 154         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 155         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 156
 157         input [A_WIDTH-1:0] A;
 158         input [B_WIDTH-1:0] B;
 159         output [Y_WIDTH-1:0] Y;
 160
 161         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 162         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 163
 164         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 165         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 166
 167         integer i;
 168         reg [WIDTH-1:0] buffer;
 169         reg overflow;
 170
 171         always @* begin
 172                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 173                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 174
 175                 for (i = 0; i < BB_WIDTH; i = i+1)
 176                         if (B[i]) begin
 177                                 if (shift_left)
 178                                         buffer = {buffer, (2**i)'b0};
 179                                 else if (2**i < WIDTH)
 180                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 181                                 else
 182                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 183                         end
 184         end
 185
 186         assign Y = buffer;
 187 endmodule
 188
 189 (* techmap_celltype = "$shift $shiftx" *)
 190 module shift_shiftx (A, B, Y);
 191         parameter A_SIGNED = 0;
 192         parameter B_SIGNED = 0;
 193         parameter A_WIDTH = 1;
 194         parameter B_WIDTH = 1;
 195         parameter Y_WIDTH = 1;
 196
 197         input [A_WIDTH-1:0] A;
 198         input [B_WIDTH-1:0] B;
 199         output [Y_WIDTH-1:0] Y;
 200
 201         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 202         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 203
 204         parameter _TECHMAP_CELLTYPE_ = "";
 205         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 206
 207         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 208         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 209
 210         integer i;
 211         reg [WIDTH-1:0] buffer;
 212         reg overflow;
 213
 214         always @* begin
 215                 overflow = 0;
 216                 buffer = {WIDTH{extbit}};
 217                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 218
 219                 if (B_WIDTH > BB_WIDTH) begin
 220                         if (B_SIGNED) begin
 221                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 222                                         if (B[i] != B[BB_WIDTH-1])
 223                                                 overflow = 1;
 224                         end else
 225                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 226                         if (overflow)
 227                                 buffer = {WIDTH{extbit}};
 228                 end
 229
 230                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 231                         if (B[i]) begin
 232                                 if (B_SIGNED && i == BB_WIDTH-1)
 233                                         buffer = {buffer, {2**i{extbit}}};
 234                                 else if (2**i < WIDTH)
 235                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 236                                 else
 237                                         buffer = {WIDTH{extbit}};
 238                         end
 239         end
 240
 241         assign Y = buffer;
 242 endmodule
 243
 244
 245 // --------------------------------------------------------
 246 // ALU Infrastructure
 247 // --------------------------------------------------------
 248
 249 module \$fa (A, B, C, X, Y);
 250         parameter WIDTH = 1;
 251
 252         input [WIDTH-1:0] A, B, C;
 253         output [WIDTH-1:0] X, Y;
 254
 255         wire [WIDTH-1:0] t1, t2, t3;
 256
 257         assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
 258         assign Y = t1 ^ C, X = t2 | t3;
 259 endmodule
 260
 261 module \$lcu (P, G, CI, CO);
 262         parameter WIDTH = 2;
 263
 264         input [WIDTH-1:0] P, G;
 265         input CI;
 266
 267         output [WIDTH-1:0] CO;
 268
 269         integer i, j;
 270         reg [WIDTH-1:0] p, g;
 271
 272         wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
 273
 274         always @* begin
 275                 p = P;
 276                 g = G;
 277
 278                 // in almost all cases CI will be constant zero
 279                 g[0] = g[0] | (p[0] & CI);
 280
 281                 // [[CITE]] Brent Kung Adder
 282                 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
 283                 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
 284
 285                 // Main tree
 286                 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
 287                         for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
 288                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 289                                 p[j] = p[j] & p[j - 2**(i-1)];
 290                         end
 291                 end
 292
 293                 // Inverse tree
 294                 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
 295                         for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
 296                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 297                                 p[j] = p[j] & p[j - 2**(i-1)];
 298                         end
 299                 end
 300         end
 301
 302         assign CO = g;
 303 endmodule
 304
 305 module \$alu (A, B, CI, BI, X, Y, CO);
 306         parameter A_SIGNED = 0;
 307         parameter B_SIGNED = 0;
 308         parameter A_WIDTH = 1;
 309         parameter B_WIDTH = 1;
 310         parameter Y_WIDTH = 1;
 311
 312         input [A_WIDTH-1:0] A;
 313         input [B_WIDTH-1:0] B;
 314         output [Y_WIDTH-1:0] X, Y;
 315
 316         input CI, BI;
 317         output [Y_WIDTH-1:0] CO;
 318
 319         wire [Y_WIDTH-1:0] A_buf, B_buf;
 320         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 321         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 322
 323         wire [Y_WIDTH-1:0] AA = A_buf;
 324         wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 325
 326         \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
 327
 328         assign X = AA ^ BB;
 329         assign Y = X ^ {CO, CI};
 330 endmodule
 331
 332
 333 // --------------------------------------------------------
 334 // ALU Cell Types: Compare, Add, Subtract
 335 // --------------------------------------------------------
 336
 337 `define ALU_COMMONS(_width, _sub) """
 338         parameter A_SIGNED = 0;
 339         parameter B_SIGNED = 0;
 340         parameter A_WIDTH = 1;
 341         parameter B_WIDTH = 1;
 342         parameter Y_WIDTH = 1;
 343
 344         localparam WIDTH = _width;
 345
 346         input [A_WIDTH-1:0] A;
 347         input [B_WIDTH-1:0] B;
 348         output [Y_WIDTH-1:0] Y;
 349
 350         wire [WIDTH-1:0] alu_x, alu_y, alu_co;
 351         wire [WIDTH:0] carry = {alu_co, |_sub};
 352
 353         \$alu #(
 354                 .A_SIGNED(A_SIGNED),
 355                 .B_SIGNED(B_SIGNED),
 356                 .A_WIDTH(A_WIDTH),
 357                 .B_WIDTH(B_WIDTH),
 358                 .Y_WIDTH(WIDTH)
 359         ) alu (
 360                 .A(A),
 361                 .B(B),
 362                 .CI(|_sub),
 363                 .BI(|_sub),
 364                 .X(alu_x),
 365                 .Y(alu_y),
 366                 .CO(alu_co)
 367         );
 368
 369         wire cf, of, zf, sf;
 370         assign cf = !carry[WIDTH];
 371         assign of = carry[WIDTH] ^ carry[WIDTH-1];
 372         assign sf = alu_y[WIDTH-1];
 373 """
 374
 375 module \$lt (A, B, Y);
 376         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 377         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 378         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 379 endmodule
 380
 381 module \$le (A, B, Y);
 382         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 383         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 384         assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
 385 endmodule
 386
 387 module \$add (A, B, Y);
 388         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 389         `ALU_COMMONS(Y_WIDTH, 0)
 390         assign Y = alu_y;
 391 endmodule
 392
 393 module \$sub (A, B, Y);
 394         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 395         `ALU_COMMONS(Y_WIDTH, 1)
 396         assign Y = alu_y;
 397 endmodule
 398
 399
 400 // --------------------------------------------------------
 401 // Multiply
 402 // --------------------------------------------------------
 403
 404 (* techmap_maccmap *)
 405 module \$macc ;
 406 endmodule
 407
 408 module \$mul (A, B, Y);
 409         parameter A_SIGNED = 0;
 410         parameter B_SIGNED = 0;
 411         parameter A_WIDTH = 1;
 412         parameter B_WIDTH = 1;
 413         parameter Y_WIDTH = 1;
 414
 415         input [A_WIDTH-1:0] A;
 416         input [B_WIDTH-1:0] B;
 417         output [Y_WIDTH-1:0] Y;
 418
 419         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
 420
 421         localparam [ 3:0] CONFIG_WIDTH_BITS = 15;
 422         localparam [ 0:0] CONFIG_IS_SIGNED = A_SIGNED && B_SIGNED;
 423         localparam [ 0:0] CONFIG_DO_SUBTRACT = 0;
 424         localparam [14:0] CONFIG_A_WIDTH = A_WIDTH;
 425         localparam [14:0] CONFIG_B_WIDTH = B_WIDTH;
 426
 427         \$macc #(
 428                 .CONFIG({CONFIG_B_WIDTH, CONFIG_A_WIDTH, CONFIG_DO_SUBTRACT, CONFIG_IS_SIGNED, CONFIG_WIDTH_BITS}),
 429                 .CONFIG_WIDTH(15 + 15 + 2 + 4),
 430                 .A_WIDTH(B_WIDTH + A_WIDTH),
 431                 .B_WIDTH(0),
 432                 .Y_WIDTH(Y_WIDTH)
 433         ) _TECHMAP_REPLACE_ (
 434                 .A({B, A}),
 435                 .B(),
 436                 .Y(Y)
 437         );
 438 endmodule
 439
 440
 441 // --------------------------------------------------------
 442 // Divide and Modulo
 443 // --------------------------------------------------------
 444
 445 module \$__div_mod_u (A, B, Y, R);
 446         parameter WIDTH = 1;
 447
 448         input [WIDTH-1:0] A, B;
 449         output [WIDTH-1:0] Y, R;
 450
 451         wire [WIDTH*WIDTH-1:0] chaindata;
 452         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 453
 454         genvar i;
 455         generate begin
 456                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 457                         wire [WIDTH-1:0] stage_in;
 458
 459                         if (i == 0) begin:cp
 460                                 assign stage_in = A;
 461                         end else begin:cp
 462                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 463                         end
 464
 465                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 466                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 467                 end
 468         end endgenerate
 469 endmodule
 470
 471 module \$__div_mod (A, B, Y, R);
 472         parameter A_SIGNED = 0;
 473         parameter B_SIGNED = 0;
 474         parameter A_WIDTH = 1;
 475         parameter B_WIDTH = 1;
 476         parameter Y_WIDTH = 1;
 477
 478         localparam WIDTH =
 479                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 480                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 481
 482         input [A_WIDTH-1:0] A;
 483         input [B_WIDTH-1:0] B;
 484         output [Y_WIDTH-1:0] Y, R;
 485
 486         wire [WIDTH-1:0] A_buf, B_buf;
 487         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 488         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 489
 490         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 491         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 492         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 493
 494         \$__div_mod_u #(
 495                 .WIDTH(WIDTH)
 496         ) div_mod_u (
 497                 .A(A_buf_u),
 498                 .B(B_buf_u),
 499                 .Y(Y_u),
 500                 .R(R_u)
 501         );
 502
 503         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 504         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 505 endmodule
 506
 507 module \$div (A, B, Y);
 508         parameter A_SIGNED = 0;
 509         parameter B_SIGNED = 0;
 510         parameter A_WIDTH = 1;
 511         parameter B_WIDTH = 1;
 512         parameter Y_WIDTH = 1;
 513
 514         input [A_WIDTH-1:0] A;
 515         input [B_WIDTH-1:0] B;
 516         output [Y_WIDTH-1:0] Y;
 517
 518         \$__div_mod #(
 519                 .A_SIGNED(A_SIGNED),
 520                 .B_SIGNED(B_SIGNED),
 521                 .A_WIDTH(A_WIDTH),
 522                 .B_WIDTH(B_WIDTH),
 523                 .Y_WIDTH(Y_WIDTH)
 524         ) div_mod (
 525                 .A(A),
 526                 .B(B),
 527                 .Y(Y)
 528         );
 529 endmodule
 530
 531 module \$mod (A, B, Y);
 532         parameter A_SIGNED = 0;
 533         parameter B_SIGNED = 0;
 534         parameter A_WIDTH = 1;
 535         parameter B_WIDTH = 1;
 536         parameter Y_WIDTH = 1;
 537
 538         input [A_WIDTH-1:0] A;
 539         input [B_WIDTH-1:0] B;
 540         output [Y_WIDTH-1:0] Y;
 541
 542         \$__div_mod #(
 543                 .A_SIGNED(A_SIGNED),
 544                 .B_SIGNED(B_SIGNED),
 545                 .A_WIDTH(A_WIDTH),
 546                 .B_WIDTH(B_WIDTH),
 547                 .Y_WIDTH(Y_WIDTH)
 548         ) div_mod (
 549                 .A(A),
 550                 .B(B),
 551                 .R(Y)
 552         );
 553 endmodule
 554
 555
 556 // --------------------------------------------------------
 557 // Power
 558 // --------------------------------------------------------
 559
 560 module \$pow (A, B, Y);
 561         parameter A_SIGNED = 0;
 562         parameter B_SIGNED = 0;
 563         parameter A_WIDTH = 1;
 564         parameter B_WIDTH = 1;
 565         parameter Y_WIDTH = 1;
 566
 567         input [A_WIDTH-1:0] A;
 568         input [B_WIDTH-1:0] B;
 569         output [Y_WIDTH-1:0] Y;
 570
 571         wire _TECHMAP_FAIL_ = 1;
 572 endmodule
 573
 574
 575 // --------------------------------------------------------
 576 // Equal and Not-Equal
 577 // --------------------------------------------------------
 578
 579 module \$eq (A, B, Y);
 580         parameter A_SIGNED = 0;
 581         parameter B_SIGNED = 0;
 582         parameter A_WIDTH = 1;
 583         parameter B_WIDTH = 1;
 584         parameter Y_WIDTH = 1;
 585
 586         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 587
 588         input [A_WIDTH-1:0] A;
 589         input [B_WIDTH-1:0] B;
 590         output [Y_WIDTH-1:0] Y;
 591
 592         wire carry, carry_sign;
 593         wire [WIDTH-1:0] A_buf, B_buf;
 594         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 595         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 596
 597         assign Y = ~|(A_buf ^ B_buf);
 598 endmodule
 599
 600 module \$ne (A, B, Y);
 601         parameter A_SIGNED = 0;
 602         parameter B_SIGNED = 0;
 603         parameter A_WIDTH = 1;
 604         parameter B_WIDTH = 1;
 605         parameter Y_WIDTH = 1;
 606
 607         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 608
 609         input [A_WIDTH-1:0] A;
 610         input [B_WIDTH-1:0] B;
 611         output [Y_WIDTH-1:0] Y;
 612
 613         wire carry, carry_sign;
 614         wire [WIDTH-1:0] A_buf, B_buf;
 615         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 616         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 617
 618         assign Y = |(A_buf ^ B_buf);
 619 endmodule
 620
 621 module \$eqx (A, B, Y);
 622         parameter A_SIGNED = 0;
 623         parameter B_SIGNED = 0;
 624         parameter A_WIDTH = 1;
 625         parameter B_WIDTH = 1;
 626         parameter Y_WIDTH = 1;
 627
 628         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 629
 630         input [A_WIDTH-1:0] A;
 631         input [B_WIDTH-1:0] B;
 632         output [Y_WIDTH-1:0] Y;
 633
 634         wire carry, carry_sign;
 635         wire [WIDTH-1:0] A_buf, B_buf;
 636         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 637         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 638
 639         assign Y = ~|(A_buf ^ B_buf);
 640 endmodule
 641
 642 module \$nex (A, B, Y);
 643         parameter A_SIGNED = 0;
 644         parameter B_SIGNED = 0;
 645         parameter A_WIDTH = 1;
 646         parameter B_WIDTH = 1;
 647         parameter Y_WIDTH = 1;
 648
 649         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 650
 651         input [A_WIDTH-1:0] A;
 652         input [B_WIDTH-1:0] B;
 653         output [Y_WIDTH-1:0] Y;
 654
 655         wire carry, carry_sign;
 656         wire [WIDTH-1:0] A_buf, B_buf;
 657         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 658         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 659
 660         assign Y = |(A_buf ^ B_buf);
 661 endmodule
 662
 663
 664 // --------------------------------------------------------
 665 // Parallel Multiplexers
 666 // --------------------------------------------------------
 667
 668 module \$pmux (A, B, S, Y);
 669         parameter WIDTH = 1;
 670         parameter S_WIDTH = 1;
 671
 672         input [WIDTH-1:0] A;
 673         input [WIDTH*S_WIDTH-1:0] B;
 674         input [S_WIDTH-1:0] S;
 675         output [WIDTH-1:0] Y;
 676
 677         wire [WIDTH-1:0] Y_B;
 678
 679         genvar i, j;
 680         generate
 681                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 682                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 683                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 684                 end:B_AND
 685                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 686                         wire [S_WIDTH-1:0] B_AND_BITS;
 687                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 688                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 689                         end:B_AND_BITS_COLLECT
 690                         assign Y_B[i] = |B_AND_BITS;
 691                 end:B_OR
 692         endgenerate
 693
 694         assign Y = |S ? Y_B : A;
 695 endmodule
 696
 697
 698 // --------------------------------------------------------
 699 // LUTs
 700 // --------------------------------------------------------
 701
 702 `ifndef NOLUT
 703 module \$lut (A, Y);
 704         parameter WIDTH = 1;
 705         parameter LUT = 0;
 706
 707         input [WIDTH-1:0] A;
 708         output Y;
 709
 710         assign Y = LUT[A];
 711 endmodule
 712 `endif
 713