techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This Verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  43 module _90_simplemap_bool_ops;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  48 module _90_simplemap_reduce_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  53 module _90_simplemap_logic_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$eq $eqx $ne $nex" *)
  58 module _90_simplemap_compare_ops;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$pos $slice $concat $mux $tribuf" *)
  63 module _90_simplemap_various;
  64 endmodule
  65
  66 (* techmap_simplemap *)
  67 (* techmap_celltype = "$sr $ff $dff $dffe $adff $dffsr $dlatch" *)
  68 module _90_simplemap_registers;
  69 endmodule
  70
  71
  72 // --------------------------------------------------------
  73 // Shift operators
  74 // --------------------------------------------------------
  75
  76 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
  77 module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
  78         parameter A_SIGNED = 0;
  79         parameter B_SIGNED = 0;
  80         parameter A_WIDTH = 1;
  81         parameter B_WIDTH = 1;
  82         parameter Y_WIDTH = 1;
  83
  84         parameter _TECHMAP_CELLTYPE_ = "";
  85         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
  86         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
  87
  88         input [A_WIDTH-1:0] A;
  89         input [B_WIDTH-1:0] B;
  90         output [Y_WIDTH-1:0] Y;
  91
  92         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
  93         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
  94
  95         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
  96         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
  97
  98         integer i;
  99         reg [WIDTH-1:0] buffer;
 100         reg overflow;
 101
 102         always @* begin
 103                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 104                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 105
 106                 for (i = 0; i < BB_WIDTH; i = i+1)
 107                         if (B[i]) begin
 108                                 if (shift_left)
 109                                         buffer = {buffer, (2**i)'b0};
 110                                 else if (2**i < WIDTH)
 111                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 112                                 else
 113                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 114                         end
 115         end
 116
 117         assign Y = buffer;
 118 endmodule
 119
 120 (* techmap_celltype = "$shift $shiftx" *)
 121 module _90_shift_shiftx (A, B, Y);
 122         parameter A_SIGNED = 0;
 123         parameter B_SIGNED = 0;
 124         parameter A_WIDTH = 1;
 125         parameter B_WIDTH = 1;
 126         parameter Y_WIDTH = 1;
 127
 128         input [A_WIDTH-1:0] A;
 129         input [B_WIDTH-1:0] B;
 130         output [Y_WIDTH-1:0] Y;
 131
 132         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 133         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 134
 135         parameter _TECHMAP_CELLTYPE_ = "";
 136         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 137
 138         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 139         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
 140
 141         integer i;
 142         reg [WIDTH-1:0] buffer;
 143         reg overflow;
 144
 145         always @* begin
 146                 overflow = 0;
 147                 buffer = {WIDTH{extbit}};
 148                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 149
 150                 if (B_WIDTH > BB_WIDTH) begin
 151                         if (B_SIGNED) begin
 152                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 153                                         if (B[i] != B[BB_WIDTH-1])
 154                                                 overflow = 1;
 155                         end else
 156                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 157                         if (overflow)
 158                                 buffer = {WIDTH{extbit}};
 159                 end
 160
 161                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 162                         if (B[i]) begin
 163                                 if (B_SIGNED && i == BB_WIDTH-1)
 164                                         buffer = {buffer, {2**i{extbit}}};
 165                                 else if (2**i < WIDTH)
 166                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 167                                 else
 168                                         buffer = {WIDTH{extbit}};
 169                         end
 170         end
 171
 172         assign Y = buffer;
 173 endmodule
 174
 175
 176 // --------------------------------------------------------
 177 // Arithmetic operators
 178 // --------------------------------------------------------
 179
 180 (* techmap_celltype = "$fa" *)
 181 module _90_fa (A, B, C, X, Y);
 182         parameter WIDTH = 1;
 183
 184         input [WIDTH-1:0] A, B, C;
 185         output [WIDTH-1:0] X, Y;
 186
 187         wire [WIDTH-1:0] t1, t2, t3;
 188
 189         assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
 190         assign Y = t1 ^ C, X = t2 | t3;
 191 endmodule
 192
 193 (* techmap_celltype = "$lcu" *)
 194 module _90_lcu (P, G, CI, CO);
 195         parameter WIDTH = 2;
 196
 197         input [WIDTH-1:0] P, G;
 198         input CI;
 199
 200         output [WIDTH-1:0] CO;
 201
 202         integer i, j;
 203         reg [WIDTH-1:0] p, g;
 204
 205         wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
 206
 207         always @* begin
 208                 p = P;
 209                 g = G;
 210
 211                 // in almost all cases CI will be constant zero
 212                 g[0] = g[0] | (p[0] & CI);
 213
 214                 // [[CITE]] Brent Kung Adder
 215                 // R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders",
 216                 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
 217
 218                 // Main tree
 219                 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
 220                         for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
 221                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 222                                 p[j] = p[j] & p[j - 2**(i-1)];
 223                         end
 224                 end
 225
 226                 // Inverse tree
 227                 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
 228                         for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
 229                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 230                                 p[j] = p[j] & p[j - 2**(i-1)];
 231                         end
 232                 end
 233         end
 234
 235         assign CO = g;
 236 endmodule
 237
 238 (* techmap_celltype = "$alu" *)
 239 module _90_alu (A, B, CI, BI, X, Y, CO);
 240         parameter A_SIGNED = 0;
 241         parameter B_SIGNED = 0;
 242         parameter A_WIDTH = 1;
 243         parameter B_WIDTH = 1;
 244         parameter Y_WIDTH = 1;
 245
 246         input [A_WIDTH-1:0] A;
 247         input [B_WIDTH-1:0] B;
 248         output [Y_WIDTH-1:0] X, Y;
 249
 250         input CI, BI;
 251         output [Y_WIDTH-1:0] CO;
 252
 253         wire [Y_WIDTH-1:0] A_buf, B_buf;
 254         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 255         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 256
 257         wire [Y_WIDTH-1:0] AA = A_buf;
 258         wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 259
 260         \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
 261
 262         assign X = AA ^ BB;
 263         assign Y = X ^ {CO, CI};
 264 endmodule
 265
 266 (* techmap_maccmap *)
 267 (* techmap_celltype = "$macc" *)
 268 module _90_macc;
 269 endmodule
 270
 271 (* techmap_wrap = "alumacc" *)
 272 (* techmap_celltype = "$lt $le $ge $gt $add $sub $neg $mul" *)
 273 module _90_alumacc;
 274 endmodule
 275
 276
 277 // --------------------------------------------------------
 278 // Divide and Modulo
 279 // --------------------------------------------------------
 280
 281 module \$__div_mod_u (A, B, Y, R);
 282         parameter WIDTH = 1;
 283
 284         input [WIDTH-1:0] A, B;
 285         output [WIDTH-1:0] Y, R;
 286
 287         wire [WIDTH*WIDTH-1:0] chaindata;
 288         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 289
 290         genvar i;
 291         generate begin
 292                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 293                         wire [WIDTH-1:0] stage_in;
 294
 295                         if (i == 0) begin:cp
 296                                 assign stage_in = A;
 297                         end else begin:cp
 298                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 299                         end
 300
 301                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 302                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 303                 end
 304         end endgenerate
 305 endmodule
 306
 307 module \$__div_mod (A, B, Y, R);
 308         parameter A_SIGNED = 0;
 309         parameter B_SIGNED = 0;
 310         parameter A_WIDTH = 1;
 311         parameter B_WIDTH = 1;
 312         parameter Y_WIDTH = 1;
 313
 314         localparam WIDTH =
 315                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 316                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 317
 318         input [A_WIDTH-1:0] A;
 319         input [B_WIDTH-1:0] B;
 320         output [Y_WIDTH-1:0] Y, R;
 321
 322         wire [WIDTH-1:0] A_buf, B_buf;
 323         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 324         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 325
 326         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 327         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 328         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 329
 330         \$__div_mod_u #(
 331                 .WIDTH(WIDTH)
 332         ) div_mod_u (
 333                 .A(A_buf_u),
 334                 .B(B_buf_u),
 335                 .Y(Y_u),
 336                 .R(R_u)
 337         );
 338
 339         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 340         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 341 endmodule
 342
 343 (* techmap_celltype = "$div" *)
 344 module _90_div (A, B, Y);
 345         parameter A_SIGNED = 0;
 346         parameter B_SIGNED = 0;
 347         parameter A_WIDTH = 1;
 348         parameter B_WIDTH = 1;
 349         parameter Y_WIDTH = 1;
 350
 351         input [A_WIDTH-1:0] A;
 352         input [B_WIDTH-1:0] B;
 353         output [Y_WIDTH-1:0] Y;
 354
 355         \$__div_mod #(
 356                 .A_SIGNED(A_SIGNED),
 357                 .B_SIGNED(B_SIGNED),
 358                 .A_WIDTH(A_WIDTH),
 359                 .B_WIDTH(B_WIDTH),
 360                 .Y_WIDTH(Y_WIDTH)
 361         ) div_mod (
 362                 .A(A),
 363                 .B(B),
 364                 .Y(Y)
 365         );
 366 endmodule
 367
 368 (* techmap_celltype = "$mod" *)
 369 module _90_mod (A, B, Y);
 370         parameter A_SIGNED = 0;
 371         parameter B_SIGNED = 0;
 372         parameter A_WIDTH = 1;
 373         parameter B_WIDTH = 1;
 374         parameter Y_WIDTH = 1;
 375
 376         input [A_WIDTH-1:0] A;
 377         input [B_WIDTH-1:0] B;
 378         output [Y_WIDTH-1:0] Y;
 379
 380         \$__div_mod #(
 381                 .A_SIGNED(A_SIGNED),
 382                 .B_SIGNED(B_SIGNED),
 383                 .A_WIDTH(A_WIDTH),
 384                 .B_WIDTH(B_WIDTH),
 385                 .Y_WIDTH(Y_WIDTH)
 386         ) div_mod (
 387                 .A(A),
 388                 .B(B),
 389                 .R(Y)
 390         );
 391 endmodule
 392
 393
 394 // --------------------------------------------------------
 395 // Power
 396 // --------------------------------------------------------
 397
 398 (* techmap_celltype = "$pow" *)
 399 module _90_pow (A, B, Y);
 400         parameter A_SIGNED = 0;
 401         parameter B_SIGNED = 0;
 402         parameter A_WIDTH = 1;
 403         parameter B_WIDTH = 1;
 404         parameter Y_WIDTH = 1;
 405
 406         input [A_WIDTH-1:0] A;
 407         input [B_WIDTH-1:0] B;
 408         output [Y_WIDTH-1:0] Y;
 409
 410         wire _TECHMAP_FAIL_ = 1;
 411 endmodule
 412
 413
 414 // --------------------------------------------------------
 415 // Parallel Multiplexers
 416 // --------------------------------------------------------
 417
 418 (* techmap_celltype = "$pmux" *)
 419 module _90_pmux (A, B, S, Y);
 420         parameter WIDTH = 1;
 421         parameter S_WIDTH = 1;
 422
 423         input [WIDTH-1:0] A;
 424         input [WIDTH*S_WIDTH-1:0] B;
 425         input [S_WIDTH-1:0] S;
 426         output [WIDTH-1:0] Y;
 427
 428         wire [WIDTH-1:0] Y_B;
 429
 430         genvar i, j;
 431         generate
 432                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 433                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 434                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 435                 end:B_AND
 436                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 437                         wire [S_WIDTH-1:0] B_AND_BITS;
 438                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 439                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 440                         end:B_AND_BITS_COLLECT
 441                         assign Y_B[i] = |B_AND_BITS;
 442                 end:B_OR
 443         endgenerate
 444
 445         assign Y = |S ? Y_B : A;
 446 endmodule
 447
 448
 449 // --------------------------------------------------------
 450 // LUTs
 451 // --------------------------------------------------------
 452
 453 `ifndef NOLUT
 454 (* techmap_simplemap *)
 455 (* techmap_celltype = "$lut $sop" *)
 456 module _90_lut;
 457 endmodule
 458 `endif
 459