techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_INV_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$pos $bu0" *)
  43 module simplemap_buffers;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  48 module simplemap_bool_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  53 module simplemap_reduce_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  58 module simplemap_logic_ops;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$slice $concat $mux" *)
  63 module simplemap_various;
  64 endmodule
  65
  66 (* techmap_simplemap *)
  67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  68 module simplemap_registers;
  69 endmodule
  70
  71
  72 // --------------------------------------------------------
  73 // Trivial substitutions
  74 // --------------------------------------------------------
  75
  76 module \$neg (A, Y);
  77         parameter A_SIGNED = 0;
  78         parameter A_WIDTH = 1;
  79         parameter Y_WIDTH = 1;
  80
  81         input [A_WIDTH-1:0] A;
  82         output [Y_WIDTH-1:0] Y;
  83
  84         \$sub #(
  85                 .A_SIGNED(A_SIGNED),
  86                 .B_SIGNED(A_SIGNED),
  87                 .A_WIDTH(1),
  88                 .B_WIDTH(A_WIDTH),
  89                 .Y_WIDTH(Y_WIDTH)
  90         ) _TECHMAP_REPLACE_ (
  91                 .A(1'b0),
  92                 .B(A),
  93                 .Y(Y)
  94         );
  95 endmodule
  96
  97 module \$ge (A, B, Y);
  98         parameter A_SIGNED = 0;
  99         parameter B_SIGNED = 0;
 100         parameter A_WIDTH = 1;
 101         parameter B_WIDTH = 1;
 102         parameter Y_WIDTH = 1;
 103
 104         input [A_WIDTH-1:0] A;
 105         input [B_WIDTH-1:0] B;
 106         output [Y_WIDTH-1:0] Y;
 107
 108         \$le #(
 109                 .A_SIGNED(B_SIGNED),
 110                 .B_SIGNED(A_SIGNED),
 111                 .A_WIDTH(B_WIDTH),
 112                 .B_WIDTH(A_WIDTH),
 113                 .Y_WIDTH(Y_WIDTH)
 114         ) _TECHMAP_REPLACE_ (
 115                 .A(B),
 116                 .B(A),
 117                 .Y(Y)
 118         );
 119 endmodule
 120
 121 module \$gt (A, B, Y);
 122         parameter A_SIGNED = 0;
 123         parameter B_SIGNED = 0;
 124         parameter A_WIDTH = 1;
 125         parameter B_WIDTH = 1;
 126         parameter Y_WIDTH = 1;
 127
 128         input [A_WIDTH-1:0] A;
 129         input [B_WIDTH-1:0] B;
 130         output [Y_WIDTH-1:0] Y;
 131
 132         \$lt #(
 133                 .A_SIGNED(B_SIGNED),
 134                 .B_SIGNED(A_SIGNED),
 135                 .A_WIDTH(B_WIDTH),
 136                 .B_WIDTH(A_WIDTH),
 137                 .Y_WIDTH(Y_WIDTH)
 138         ) _TECHMAP_REPLACE_ (
 139                 .A(B),
 140                 .B(A),
 141                 .Y(Y)
 142         );
 143 endmodule
 144
 145
 146 // --------------------------------------------------------
 147 // Shift operators
 148 // --------------------------------------------------------
 149
 150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 152         parameter A_SIGNED = 0;
 153         parameter B_SIGNED = 0;
 154         parameter A_WIDTH = 1;
 155         parameter B_WIDTH = 1;
 156         parameter Y_WIDTH = 1;
 157
 158         parameter _TECHMAP_CELLTYPE_ = "";
 159         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 160         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 161
 162         input [A_WIDTH-1:0] A;
 163         input [B_WIDTH-1:0] B;
 164         output [Y_WIDTH-1:0] Y;
 165
 166         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 167         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 168
 169         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 170         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 171
 172         integer i;
 173         reg [WIDTH-1:0] buffer;
 174         reg overflow;
 175
 176         always @* begin
 177                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 178                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 179
 180                 for (i = 0; i < BB_WIDTH; i = i+1)
 181                         if (B[i]) begin
 182                                 if (shift_left)
 183                                         buffer = {buffer, (2**i)'b0};
 184                                 else if (2**i < WIDTH)
 185                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 186                                 else
 187                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 188                         end
 189         end
 190
 191         assign Y = buffer;
 192 endmodule
 193
 194 (* techmap_celltype = "$shift $shiftx" *)
 195 module shift_shiftx (A, B, Y);
 196         parameter A_SIGNED = 0;
 197         parameter B_SIGNED = 0;
 198         parameter A_WIDTH = 1;
 199         parameter B_WIDTH = 1;
 200         parameter Y_WIDTH = 1;
 201
 202         input [A_WIDTH-1:0] A;
 203         input [B_WIDTH-1:0] B;
 204         output [Y_WIDTH-1:0] Y;
 205
 206         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 207         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 208
 209         parameter _TECHMAP_CELLTYPE_ = "";
 210         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 211
 212         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 213         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 214
 215         integer i;
 216         reg [WIDTH-1:0] buffer;
 217         reg overflow;
 218
 219         always @* begin
 220                 overflow = 0;
 221                 buffer = {WIDTH{extbit}};
 222                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 223
 224                 if (B_WIDTH > BB_WIDTH) begin
 225                         if (B_SIGNED) begin
 226                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 227                                         if (B[i] != B[BB_WIDTH-1])
 228                                                 overflow = 1;
 229                         end else
 230                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 231                         if (overflow)
 232                                 buffer = {WIDTH{extbit}};
 233                 end
 234
 235                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 236                         if (B[i]) begin
 237                                 if (B_SIGNED && i == BB_WIDTH-1)
 238                                         buffer = {buffer, {2**i{extbit}}};
 239                                 else if (2**i < WIDTH)
 240                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 241                                 else
 242                                         buffer = {WIDTH{extbit}};
 243                         end
 244         end
 245
 246         assign Y = buffer;
 247 endmodule
 248
 249
 250 // --------------------------------------------------------
 251 // ALU Infrastructure
 252 // --------------------------------------------------------
 253
 254 module \$__fulladd (A, B, C, X, Y);
 255         // {X, Y} = A + B + C
 256         input A, B, C;
 257         output X, Y;
 258
 259         // {t1, t2} = A + B
 260         wire t1, t2, t3;
 261
 262         \$_AND_ gate1 ( .A(A),  .B(B),  .Y(t1) );
 263         \$_XOR_ gate2 ( .A(A),  .B(B),  .Y(t2) );
 264         \$_AND_ gate3 ( .A(t2), .B(C),  .Y(t3) );
 265         \$_XOR_ gate4 ( .A(t2), .B(C),  .Y(Y)  );
 266         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(X)  );
 267 endmodule
 268
 269 module \$__alu (A, B, Cin, Y, Cout, Csign);
 270         parameter WIDTH = 1;
 271
 272         input [WIDTH-1:0] A, B;
 273         input Cin;
 274
 275         output [WIDTH-1:0] Y;
 276         output Cout, Csign;
 277
 278         wire [WIDTH:0] carry;
 279         assign carry[0] = Cin;
 280         assign Cout = carry[WIDTH];
 281         assign Csign = carry[WIDTH-1];
 282
 283         genvar i;
 284         generate
 285                 for (i = 0; i < WIDTH; i = i + 1) begin:V
 286                         \$__fulladd adder (
 287                                 .A(A[i]),
 288                                 .B(B[i]),
 289                                 .C(carry[i]),
 290                                 .X(carry[i+1]),
 291                                 .Y(Y[i])
 292                         );
 293                 end
 294         endgenerate
 295 endmodule
 296
 297
 298 // --------------------------------------------------------
 299 // Compare cells
 300 // --------------------------------------------------------
 301
 302 module \$lt (A, B, Y);
 303         parameter A_SIGNED = 0;
 304         parameter B_SIGNED = 0;
 305         parameter A_WIDTH = 1;
 306         parameter B_WIDTH = 1;
 307         parameter Y_WIDTH = 1;
 308
 309         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 310
 311         input [A_WIDTH-1:0] A;
 312         input [B_WIDTH-1:0] B;
 313         output [Y_WIDTH-1:0] Y;
 314
 315         wire carry, carry_sign;
 316         wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
 317         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 318         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 319
 320         \$__alu #(
 321                 .WIDTH(WIDTH)
 322         ) alu (
 323                 .A(A_buf),
 324                 .B(~B_buf),
 325                 .Cin(1'b1),
 326                 .Y(Y_buf),
 327                 .Cout(carry),
 328                 .Csign(carry_sign)
 329         );
 330
 331         // ALU flags
 332         wire cf, of, zf, sf;
 333         assign cf = !carry;
 334         assign of = carry ^ carry_sign;
 335         assign zf = ~|Y_buf;
 336         assign sf = Y_buf[WIDTH-1];
 337
 338         generate
 339                 if (A_SIGNED && B_SIGNED) begin
 340                         assign Y = of != sf;
 341                 end else begin
 342                         assign Y = cf;
 343                 end
 344         endgenerate
 345 endmodule
 346
 347 module \$le (A, B, Y);
 348         parameter A_SIGNED = 0;
 349         parameter B_SIGNED = 0;
 350         parameter A_WIDTH = 1;
 351         parameter B_WIDTH = 1;
 352         parameter Y_WIDTH = 1;
 353
 354         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 355
 356         input [A_WIDTH-1:0] A;
 357         input [B_WIDTH-1:0] B;
 358         output [Y_WIDTH-1:0] Y;
 359
 360         wire carry, carry_sign;
 361         wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
 362         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 363         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 364
 365         \$__alu #(
 366                 .WIDTH(WIDTH)
 367         ) alu (
 368                 .A(A_buf),
 369                 .B(~B_buf),
 370                 .Cin(1'b1),
 371                 .Y(Y_buf),
 372                 .Cout(carry),
 373                 .Csign(carry_sign)
 374         );
 375
 376         // ALU flags
 377         wire cf, of, zf, sf;
 378         assign cf = !carry;
 379         assign of = carry ^ carry_sign;
 380         assign zf = ~|Y_buf;
 381         assign sf = Y_buf[WIDTH-1];
 382
 383         generate
 384                 if (A_SIGNED && B_SIGNED) begin
 385                         assign Y = zf || (of != sf);
 386                 end else begin
 387                         assign Y = zf || cf;
 388                 end
 389         endgenerate
 390 endmodule
 391
 392
 393 // --------------------------------------------------------
 394 // Add and Subtract
 395 // --------------------------------------------------------
 396
 397 module \$add (A, B, Y);
 398         parameter A_SIGNED = 0;
 399         parameter B_SIGNED = 0;
 400         parameter A_WIDTH = 1;
 401         parameter B_WIDTH = 1;
 402         parameter Y_WIDTH = 1;
 403
 404         input [A_WIDTH-1:0] A;
 405         input [B_WIDTH-1:0] B;
 406         output [Y_WIDTH-1:0] Y;
 407
 408         wire [Y_WIDTH-1:0] A_buf, B_buf;
 409         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 410         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 411
 412         \$__alu #(
 413                 .WIDTH(Y_WIDTH)
 414         ) alu (
 415                 .A(A_buf),
 416                 .B(B_buf),
 417                 .Cin(1'b0),
 418                 .Y(Y)
 419         );
 420 endmodule
 421
 422 module \$sub (A, B, Y);
 423         parameter A_SIGNED = 0;
 424         parameter B_SIGNED = 0;
 425         parameter A_WIDTH = 1;
 426         parameter B_WIDTH = 1;
 427         parameter Y_WIDTH = 1;
 428
 429         input [A_WIDTH-1:0] A;
 430         input [B_WIDTH-1:0] B;
 431         output [Y_WIDTH-1:0] Y;
 432
 433         wire [Y_WIDTH-1:0] A_buf, B_buf;
 434         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 435         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 436
 437         \$__alu #(
 438                 .WIDTH(Y_WIDTH)
 439         ) alu (
 440                 .A(A_buf),
 441                 .B(~B_buf),
 442                 .Cin(1'b1),
 443                 .Y(Y)
 444         );
 445 endmodule
 446
 447
 448 // --------------------------------------------------------
 449 // Multiply
 450 // --------------------------------------------------------
 451
 452 module \$__arraymul (A, B, Y);
 453         parameter WIDTH = 8;
 454         input [WIDTH-1:0] A, B;
 455         output [WIDTH-1:0] Y;
 456
 457         wire [WIDTH*WIDTH-1:0] partials;
 458
 459         genvar i;
 460         assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
 461         generate for (i = 1; i < WIDTH; i = i+1) begin:gen
 462                 assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
 463         end endgenerate
 464
 465         assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
 466 endmodule
 467
 468 module \$mul (A, B, Y);
 469         parameter A_SIGNED = 0;
 470         parameter B_SIGNED = 0;
 471         parameter A_WIDTH = 1;
 472         parameter B_WIDTH = 1;
 473         parameter Y_WIDTH = 1;
 474
 475         input [A_WIDTH-1:0] A;
 476         input [B_WIDTH-1:0] B;
 477         output [Y_WIDTH-1:0] Y;
 478
 479         wire [Y_WIDTH-1:0] A_buf, B_buf;
 480         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 481         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 482
 483         \$__arraymul #(
 484                 .WIDTH(Y_WIDTH)
 485         ) arraymul (
 486                 .A(A_buf),
 487                 .B(B_buf),
 488                 .Y(Y)
 489         );
 490 endmodule
 491
 492
 493 // --------------------------------------------------------
 494 // Divide and Modulo
 495 // --------------------------------------------------------
 496
 497 module \$__div_mod_u (A, B, Y, R);
 498         parameter WIDTH = 1;
 499
 500         input [WIDTH-1:0] A, B;
 501         output [WIDTH-1:0] Y, R;
 502
 503         wire [WIDTH*WIDTH-1:0] chaindata;
 504         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 505
 506         genvar i;
 507         generate begin
 508                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 509                         wire [WIDTH-1:0] stage_in;
 510
 511                         if (i == 0) begin:cp
 512                                 assign stage_in = A;
 513                         end else begin:cp
 514                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 515                         end
 516
 517                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 518                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 519                 end
 520         end endgenerate
 521 endmodule
 522
 523 module \$__div_mod (A, B, Y, R);
 524         parameter A_SIGNED = 0;
 525         parameter B_SIGNED = 0;
 526         parameter A_WIDTH = 1;
 527         parameter B_WIDTH = 1;
 528         parameter Y_WIDTH = 1;
 529
 530         localparam WIDTH =
 531                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 532                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 533
 534         input [A_WIDTH-1:0] A;
 535         input [B_WIDTH-1:0] B;
 536         output [Y_WIDTH-1:0] Y, R;
 537
 538         wire [WIDTH-1:0] A_buf, B_buf;
 539         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 540         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 541
 542         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 543         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 544         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 545
 546         \$__div_mod_u #(
 547                 .WIDTH(WIDTH)
 548         ) div_mod_u (
 549                 .A(A_buf_u),
 550                 .B(B_buf_u),
 551                 .Y(Y_u),
 552                 .R(R_u)
 553         );
 554
 555         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 556         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 557 endmodule
 558
 559 module \$div (A, B, Y);
 560         parameter A_SIGNED = 0;
 561         parameter B_SIGNED = 0;
 562         parameter A_WIDTH = 1;
 563         parameter B_WIDTH = 1;
 564         parameter Y_WIDTH = 1;
 565
 566         input [A_WIDTH-1:0] A;
 567         input [B_WIDTH-1:0] B;
 568         output [Y_WIDTH-1:0] Y;
 569
 570         \$__div_mod #(
 571                 .A_SIGNED(A_SIGNED),
 572                 .B_SIGNED(B_SIGNED),
 573                 .A_WIDTH(A_WIDTH),
 574                 .B_WIDTH(B_WIDTH),
 575                 .Y_WIDTH(Y_WIDTH)
 576         ) div_mod (
 577                 .A(A),
 578                 .B(B),
 579                 .Y(Y)
 580         );
 581 endmodule
 582
 583 module \$mod (A, B, Y);
 584         parameter A_SIGNED = 0;
 585         parameter B_SIGNED = 0;
 586         parameter A_WIDTH = 1;
 587         parameter B_WIDTH = 1;
 588         parameter Y_WIDTH = 1;
 589
 590         input [A_WIDTH-1:0] A;
 591         input [B_WIDTH-1:0] B;
 592         output [Y_WIDTH-1:0] Y;
 593
 594         \$__div_mod #(
 595                 .A_SIGNED(A_SIGNED),
 596                 .B_SIGNED(B_SIGNED),
 597                 .A_WIDTH(A_WIDTH),
 598                 .B_WIDTH(B_WIDTH),
 599                 .Y_WIDTH(Y_WIDTH)
 600         ) div_mod (
 601                 .A(A),
 602                 .B(B),
 603                 .R(Y)
 604         );
 605 endmodule
 606
 607
 608 // --------------------------------------------------------
 609 // Power
 610 // --------------------------------------------------------
 611
 612 module \$pow (A, B, Y);
 613         parameter A_SIGNED = 0;
 614         parameter B_SIGNED = 0;
 615         parameter A_WIDTH = 1;
 616         parameter B_WIDTH = 1;
 617         parameter Y_WIDTH = 1;
 618
 619         input [A_WIDTH-1:0] A;
 620         input [B_WIDTH-1:0] B;
 621         output [Y_WIDTH-1:0] Y;
 622
 623         wire _TECHMAP_FAIL_ = 1;
 624 endmodule
 625
 626
 627 // --------------------------------------------------------
 628 // Equal and Not-Equal
 629 // --------------------------------------------------------
 630
 631 module \$eq (A, B, Y);
 632         parameter A_SIGNED = 0;
 633         parameter B_SIGNED = 0;
 634         parameter A_WIDTH = 1;
 635         parameter B_WIDTH = 1;
 636         parameter Y_WIDTH = 1;
 637
 638         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 639
 640         input [A_WIDTH-1:0] A;
 641         input [B_WIDTH-1:0] B;
 642         output [Y_WIDTH-1:0] Y;
 643
 644         wire carry, carry_sign;
 645         wire [WIDTH-1:0] A_buf, B_buf;
 646         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 647         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 648
 649         assign Y = ~|(A_buf ^ B_buf);
 650 endmodule
 651
 652 module \$ne (A, B, Y);
 653         parameter A_SIGNED = 0;
 654         parameter B_SIGNED = 0;
 655         parameter A_WIDTH = 1;
 656         parameter B_WIDTH = 1;
 657         parameter Y_WIDTH = 1;
 658
 659         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 660
 661         input [A_WIDTH-1:0] A;
 662         input [B_WIDTH-1:0] B;
 663         output [Y_WIDTH-1:0] Y;
 664
 665         wire carry, carry_sign;
 666         wire [WIDTH-1:0] A_buf, B_buf;
 667         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 668         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 669
 670         assign Y = |(A_buf ^ B_buf);
 671 endmodule
 672
 673 module \$eqx (A, B, Y);
 674         parameter A_SIGNED = 0;
 675         parameter B_SIGNED = 0;
 676         parameter A_WIDTH = 1;
 677         parameter B_WIDTH = 1;
 678         parameter Y_WIDTH = 1;
 679
 680         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 681
 682         input [A_WIDTH-1:0] A;
 683         input [B_WIDTH-1:0] B;
 684         output [Y_WIDTH-1:0] Y;
 685
 686         wire carry, carry_sign;
 687         wire [WIDTH-1:0] A_buf, B_buf;
 688         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 689         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 690
 691         assign Y = ~|(A_buf ^ B_buf);
 692 endmodule
 693
 694 module \$nex (A, B, Y);
 695         parameter A_SIGNED = 0;
 696         parameter B_SIGNED = 0;
 697         parameter A_WIDTH = 1;
 698         parameter B_WIDTH = 1;
 699         parameter Y_WIDTH = 1;
 700
 701         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 702
 703         input [A_WIDTH-1:0] A;
 704         input [B_WIDTH-1:0] B;
 705         output [Y_WIDTH-1:0] Y;
 706
 707         wire carry, carry_sign;
 708         wire [WIDTH-1:0] A_buf, B_buf;
 709         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 710         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 711
 712         assign Y = |(A_buf ^ B_buf);
 713 endmodule
 714
 715
 716 // --------------------------------------------------------
 717 // Parallel Multiplexers
 718 // --------------------------------------------------------
 719
 720 module \$pmux (A, B, S, Y);
 721         parameter WIDTH = 1;
 722         parameter S_WIDTH = 1;
 723
 724         input [WIDTH-1:0] A;
 725         input [WIDTH*S_WIDTH-1:0] B;
 726         input [S_WIDTH-1:0] S;
 727         output [WIDTH-1:0] Y;
 728
 729         wire [WIDTH-1:0] Y_B;
 730
 731         genvar i, j;
 732         generate
 733                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 734                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 735                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 736                 end:B_AND
 737                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 738                         wire [S_WIDTH-1:0] B_AND_BITS;
 739                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 740                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 741                         end:B_AND_BITS_COLLECT
 742                         assign Y_B[i] = |B_AND_BITS;
 743                 end:B_OR
 744         endgenerate
 745
 746         assign Y = |S ? Y_B : A;
 747 endmodule
 748
 749 module \$safe_pmux (A, B, S, Y);
 750         parameter WIDTH = 1;
 751         parameter S_WIDTH = 1;
 752
 753         input [WIDTH-1:0] A;
 754         input [WIDTH*S_WIDTH-1:0] B;
 755         input [S_WIDTH-1:0] S;
 756         output [WIDTH-1:0] Y;
 757
 758         wire [S_WIDTH-1:0] status_found_first;
 759         wire [S_WIDTH-1:0] status_found_second;
 760
 761         genvar i;
 762         generate
 763                 for (i = 0; i < S_WIDTH; i = i + 1) begin:GEN1
 764                         wire pre_first;
 765                         if (i > 0) begin:GEN2
 766                                 assign pre_first = status_found_first[i-1];
 767                         end:GEN2 else begin:GEN3
 768                                 assign pre_first = 0;
 769                         end:GEN3
 770                         assign status_found_first[i] = pre_first | S[i];
 771                         assign status_found_second[i] = pre_first & S[i];
 772                 end:GEN1
 773         endgenerate
 774
 775         \$pmux #(
 776                 .WIDTH(WIDTH),
 777                 .S_WIDTH(S_WIDTH)
 778         ) pmux_cell (
 779                 .A(A),
 780                 .B(B),
 781                 .S(S & {S_WIDTH{~|status_found_second}}),
 782                 .Y(Y)
 783         );
 784 endmodule
 785