2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The internal logic cell technology mapper.
22 * This verilog library contains the mapping of internal cells (e.g. $not with
23 * variable bit width) to the internal logic cells (such as the single bit $_INV_
24 * gate). Usually this logic network is then mapped to the actual technology
25 * using e.g. the "abc" pass.
27 * Note that this library does not map $mem cells. They must be mapped to logic
28 * and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
29 * which is of course highly recommended for larger memories.)
33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
37 // --------------------------------------------------------
38 // Use simplemap for trivial cell types
39 // --------------------------------------------------------
41 (* techmap_simplemap *)
42 (* techmap_celltype = "$pos $bu0" *)
43 module simplemap_buffers;
46 (* techmap_simplemap *)
47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
48 module simplemap_bool_ops;
51 (* techmap_simplemap *)
52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
53 module simplemap_reduce_ops;
56 (* techmap_simplemap *)
57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
58 module simplemap_logic_ops;
61 (* techmap_simplemap *)
62 (* techmap_celltype = "$slice $concat $mux" *)
63 module simplemap_various;
66 (* techmap_simplemap *)
67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
68 module simplemap_registers;
72 // --------------------------------------------------------
73 // Trivial substitutions
74 // --------------------------------------------------------
77 parameter A_SIGNED = 0;
78 parameter A_WIDTH = 1;
79 parameter Y_WIDTH = 1;
81 input [A_WIDTH-1:0] A;
82 output [Y_WIDTH-1:0] Y;
97 module \$ge (A, B, Y);
98 parameter A_SIGNED = 0;
99 parameter B_SIGNED = 0;
100 parameter A_WIDTH = 1;
101 parameter B_WIDTH = 1;
102 parameter Y_WIDTH = 1;
104 input [A_WIDTH-1:0] A;
105 input [B_WIDTH-1:0] B;
106 output [Y_WIDTH-1:0] Y;
114 ) _TECHMAP_REPLACE_ (
121 module \$gt (A, B, Y);
122 parameter A_SIGNED = 0;
123 parameter B_SIGNED = 0;
124 parameter A_WIDTH = 1;
125 parameter B_WIDTH = 1;
126 parameter Y_WIDTH = 1;
128 input [A_WIDTH-1:0] A;
129 input [B_WIDTH-1:0] B;
130 output [Y_WIDTH-1:0] Y;
138 ) _TECHMAP_REPLACE_ (
146 // --------------------------------------------------------
148 // --------------------------------------------------------
150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
152 parameter A_SIGNED = 0;
153 parameter B_SIGNED = 0;
154 parameter A_WIDTH = 1;
155 parameter B_WIDTH = 1;
156 parameter Y_WIDTH = 1;
158 parameter _TECHMAP_CELLTYPE_ = "";
159 localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
160 localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
162 input [A_WIDTH-1:0] A;
163 input [B_WIDTH-1:0] B;
164 output [Y_WIDTH-1:0] Y;
166 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
167 localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
169 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
170 wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
173 reg [WIDTH-1:0] buffer;
177 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
178 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
180 for (i = 0; i < BB_WIDTH; i = i+1)
183 buffer = {buffer, (2**i)'b0};
184 else if (2**i < WIDTH)
185 buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
187 buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
194 (* techmap_celltype = "$shift $shiftx" *)
195 module shift_shiftx (A, B, Y);
196 parameter A_SIGNED = 0;
197 parameter B_SIGNED = 0;
198 parameter A_WIDTH = 1;
199 parameter B_WIDTH = 1;
200 parameter Y_WIDTH = 1;
202 input [A_WIDTH-1:0] A;
203 input [B_WIDTH-1:0] B;
204 output [Y_WIDTH-1:0] Y;
206 localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
207 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
209 parameter _TECHMAP_CELLTYPE_ = "";
210 localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
212 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
213 wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
216 reg [WIDTH-1:0] buffer;
221 buffer = {WIDTH{extbit}};
222 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
224 if (B_WIDTH > BB_WIDTH) begin
226 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
227 if (B[i] != B[BB_WIDTH-1])
230 overflow = |B[B_WIDTH-1:BB_WIDTH];
232 buffer = {WIDTH{extbit}};
235 for (i = BB_WIDTH-1; i >= 0; i = i-1)
237 if (B_SIGNED && i == BB_WIDTH-1)
238 buffer = {buffer, {2**i{extbit}}};
239 else if (2**i < WIDTH)
240 buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
242 buffer = {WIDTH{extbit}};
250 // --------------------------------------------------------
251 // ALU Infrastructure
252 // --------------------------------------------------------
254 module \$__alu_ripple (A, B, CI, Y, CO, CS);
257 input [WIDTH-1:0] A, B;
258 output [WIDTH-1:0] Y;
263 wire [WIDTH:0] carry;
264 assign carry[0] = CI;
265 assign CO = carry[WIDTH];
266 assign CS = carry[WIDTH-1];
270 for (i = 0; i < WIDTH; i = i+1)
272 // {x, y} = a + b + c
276 \$_AND_ gate1 ( .A(a), .B(b), .Y(t1) );
277 \$_XOR_ gate2 ( .A(a), .B(b), .Y(t2) );
278 \$_AND_ gate3 ( .A(t2), .B(c), .Y(t3) );
279 \$_XOR_ gate4 ( .A(t2), .B(c), .Y(y) );
280 \$_OR_ gate5 ( .A(t1), .B(t3), .Y(x) );
282 assign a = A[i], b = B[i], c = carry[i];
283 assign carry[i+1] = x, Y[i] = y;
288 module \$__lcu_simple (P, G, CI, CO, PG, GG);
291 input [WIDTH-1:0] P, G;
294 output reg [WIDTH:0] CO;
297 wire [1023:0] _TECHMAP_DO_ = "proc;;";
305 for (i = 0; i < WIDTH; i = i+1) begin
308 for (j = i+1; j < WIDTH; j = j+1)
310 GG = GG || &tmp[WIDTH-1:i];
314 for (i = 0; i < WIDTH; i = i+1)
315 CO[i+1] = G[i] | (P[i] & CO[i]);
319 module \$__lcu (P, G, CI, CO, PG, GG);
322 function integer get_group_size;
325 while (4 * get_group_size < WIDTH)
326 get_group_size = 4 * get_group_size;
330 input [WIDTH-1:0] P, G;
338 if (WIDTH <= 4) begin
339 \$__lcu_simple #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO), .PG(PG), .GG(GG));
341 localparam GROUP_SIZE = get_group_size();
342 localparam GROUPS_NUM = (WIDTH + GROUP_SIZE - 1) / GROUP_SIZE;
344 wire [GROUPS_NUM-1:0] groups_p, groups_g;
345 wire [GROUPS_NUM:0] groups_ci;
347 for (i = 0; i < GROUPS_NUM; i = i+1) begin:V
348 localparam g_size = `MIN(GROUP_SIZE, WIDTH - i*GROUP_SIZE);
349 localparam g_offset = i*GROUP_SIZE;
350 wire [g_size:0] g_co;
352 \$__lcu #(.WIDTH(g_size)) g (.P(P[g_offset +: g_size]), .G(G[g_offset +: g_size]),
353 .CI(groups_ci[i]), .CO(g_co), .PG(groups_p[i]), .GG(groups_g[i]));
354 assign CO[g_offset+1 +: g_size] = g_co[1 +: g_size];
357 \$__lcu_simple #(.WIDTH(GROUPS_NUM)) super_lcu (.P(groups_p), .G(groups_g), .CI(CI), .CO(groups_ci), .PG(PG), .GG(GG));
364 module \$__alu_lookahead (A, B, CI, Y, CO, CS);
367 input [WIDTH-1:0] A, B;
368 output [WIDTH-1:0] Y;
373 wire [WIDTH-1:0] P, G;
376 assign CO = C[WIDTH];
377 assign CS = C[WIDTH-1];
381 for (i = 0; i < WIDTH; i = i+1)
383 wire a, b, c, p, g, y;
385 \$_AND_ gate1 ( .A(a), .B(b), .Y(g) );
386 \$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
387 \$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
389 assign a = A[i], b = B[i], c = C[i];
390 assign P[i] = p, G[i] = g, Y[i] = y;
394 \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
397 module \$__alu (A, B, CI, S, Y, CO, CS);
398 parameter A_SIGNED = 0;
399 parameter B_SIGNED = 0;
400 parameter A_WIDTH = 1;
401 parameter B_WIDTH = 1;
402 parameter Y_WIDTH = 1;
404 input [A_WIDTH-1:0] A;
405 input [B_WIDTH-1:0] B;
406 output [Y_WIDTH-1:0] Y;
408 // carry in, sub, carry out, carry sign
412 wire [Y_WIDTH-1:0] A_buf, B_buf;
413 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
414 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
417 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
419 if (Y_WIDTH <= 4) begin
420 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
422 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
428 // --------------------------------------------------------
429 // ALU Cell Types: Compare, Add, Subtract
430 // --------------------------------------------------------
432 `define ALU_COMMONS(_width, _ci, _s) """
433 parameter A_SIGNED = 0;
434 parameter B_SIGNED = 0;
435 parameter A_WIDTH = 1;
436 parameter B_WIDTH = 1;
437 parameter Y_WIDTH = 1;
439 localparam WIDTH = _width;
441 input [A_WIDTH-1:0] A;
442 input [B_WIDTH-1:0] B;
443 output [Y_WIDTH-1:0] Y;
446 wire [WIDTH-1:0] alu_y;
466 assign of = alu_co ^ alu_cs;
468 assign sf = alu_y[WIDTH-1];
471 module \$lt (A, B, Y);
472 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
473 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
474 assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
477 module \$le (A, B, Y);
478 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
479 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
480 assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
483 module \$add (A, B, Y);
484 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
485 `ALU_COMMONS(Y_WIDTH, 0, 0)
489 module \$sub (A, B, Y);
490 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
491 `ALU_COMMONS(Y_WIDTH, 1, 1)
496 // --------------------------------------------------------
498 // --------------------------------------------------------
500 module \$__arraymul (A, B, Y);
502 input [WIDTH-1:0] A, B;
503 output [WIDTH-1:0] Y;
505 wire [WIDTH*WIDTH-1:0] partials;
508 assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
509 generate for (i = 1; i < WIDTH; i = i+1) begin:gen
510 assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
513 assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
516 module \$mul (A, B, Y);
517 parameter A_SIGNED = 0;
518 parameter B_SIGNED = 0;
519 parameter A_WIDTH = 1;
520 parameter B_WIDTH = 1;
521 parameter Y_WIDTH = 1;
523 input [A_WIDTH-1:0] A;
524 input [B_WIDTH-1:0] B;
525 output [Y_WIDTH-1:0] Y;
527 wire [Y_WIDTH-1:0] A_buf, B_buf;
528 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
529 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
541 // --------------------------------------------------------
543 // --------------------------------------------------------
545 module \$__div_mod_u (A, B, Y, R);
548 input [WIDTH-1:0] A, B;
549 output [WIDTH-1:0] Y, R;
551 wire [WIDTH*WIDTH-1:0] chaindata;
552 assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
556 for (i = 0; i < WIDTH; i=i+1) begin:stage
557 wire [WIDTH-1:0] stage_in;
562 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
565 assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
566 assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
571 module \$__div_mod (A, B, Y, R);
572 parameter A_SIGNED = 0;
573 parameter B_SIGNED = 0;
574 parameter A_WIDTH = 1;
575 parameter B_WIDTH = 1;
576 parameter Y_WIDTH = 1;
579 A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
580 B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
582 input [A_WIDTH-1:0] A;
583 input [B_WIDTH-1:0] B;
584 output [Y_WIDTH-1:0] Y, R;
586 wire [WIDTH-1:0] A_buf, B_buf;
587 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
588 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
590 wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
591 assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
592 assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
603 assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
604 assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
607 module \$div (A, B, Y);
608 parameter A_SIGNED = 0;
609 parameter B_SIGNED = 0;
610 parameter A_WIDTH = 1;
611 parameter B_WIDTH = 1;
612 parameter Y_WIDTH = 1;
614 input [A_WIDTH-1:0] A;
615 input [B_WIDTH-1:0] B;
616 output [Y_WIDTH-1:0] Y;
631 module \$mod (A, B, Y);
632 parameter A_SIGNED = 0;
633 parameter B_SIGNED = 0;
634 parameter A_WIDTH = 1;
635 parameter B_WIDTH = 1;
636 parameter Y_WIDTH = 1;
638 input [A_WIDTH-1:0] A;
639 input [B_WIDTH-1:0] B;
640 output [Y_WIDTH-1:0] Y;
656 // --------------------------------------------------------
658 // --------------------------------------------------------
660 module \$pow (A, B, Y);
661 parameter A_SIGNED = 0;
662 parameter B_SIGNED = 0;
663 parameter A_WIDTH = 1;
664 parameter B_WIDTH = 1;
665 parameter Y_WIDTH = 1;
667 input [A_WIDTH-1:0] A;
668 input [B_WIDTH-1:0] B;
669 output [Y_WIDTH-1:0] Y;
671 wire _TECHMAP_FAIL_ = 1;
675 // --------------------------------------------------------
676 // Equal and Not-Equal
677 // --------------------------------------------------------
679 module \$eq (A, B, Y);
680 parameter A_SIGNED = 0;
681 parameter B_SIGNED = 0;
682 parameter A_WIDTH = 1;
683 parameter B_WIDTH = 1;
684 parameter Y_WIDTH = 1;
686 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
688 input [A_WIDTH-1:0] A;
689 input [B_WIDTH-1:0] B;
690 output [Y_WIDTH-1:0] Y;
692 wire carry, carry_sign;
693 wire [WIDTH-1:0] A_buf, B_buf;
694 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
695 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
697 assign Y = ~|(A_buf ^ B_buf);
700 module \$ne (A, B, Y);
701 parameter A_SIGNED = 0;
702 parameter B_SIGNED = 0;
703 parameter A_WIDTH = 1;
704 parameter B_WIDTH = 1;
705 parameter Y_WIDTH = 1;
707 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
709 input [A_WIDTH-1:0] A;
710 input [B_WIDTH-1:0] B;
711 output [Y_WIDTH-1:0] Y;
713 wire carry, carry_sign;
714 wire [WIDTH-1:0] A_buf, B_buf;
715 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
716 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
718 assign Y = |(A_buf ^ B_buf);
721 module \$eqx (A, B, Y);
722 parameter A_SIGNED = 0;
723 parameter B_SIGNED = 0;
724 parameter A_WIDTH = 1;
725 parameter B_WIDTH = 1;
726 parameter Y_WIDTH = 1;
728 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
730 input [A_WIDTH-1:0] A;
731 input [B_WIDTH-1:0] B;
732 output [Y_WIDTH-1:0] Y;
734 wire carry, carry_sign;
735 wire [WIDTH-1:0] A_buf, B_buf;
736 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
737 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
739 assign Y = ~|(A_buf ^ B_buf);
742 module \$nex (A, B, Y);
743 parameter A_SIGNED = 0;
744 parameter B_SIGNED = 0;
745 parameter A_WIDTH = 1;
746 parameter B_WIDTH = 1;
747 parameter Y_WIDTH = 1;
749 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
751 input [A_WIDTH-1:0] A;
752 input [B_WIDTH-1:0] B;
753 output [Y_WIDTH-1:0] Y;
755 wire carry, carry_sign;
756 wire [WIDTH-1:0] A_buf, B_buf;
757 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
758 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
760 assign Y = |(A_buf ^ B_buf);
764 // --------------------------------------------------------
765 // Parallel Multiplexers
766 // --------------------------------------------------------
768 module \$pmux (A, B, S, Y);
770 parameter S_WIDTH = 1;
773 input [WIDTH*S_WIDTH-1:0] B;
774 input [S_WIDTH-1:0] S;
775 output [WIDTH-1:0] Y;
777 wire [WIDTH-1:0] Y_B;
781 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
782 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
783 assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
785 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
786 wire [S_WIDTH-1:0] B_AND_BITS;
787 for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
788 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
789 end:B_AND_BITS_COLLECT
790 assign Y_B[i] = |B_AND_BITS;
794 assign Y = |S ? Y_B : A;