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Added $alu cell type
[yosys.git] / techlibs / common / techmap.v
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The internal logic cell technology mapper.
21 *
22 * This verilog library contains the mapping of internal cells (e.g. $not with
23 * variable bit width) to the internal logic cells (such as the single bit $_NOT_
24 * gate). Usually this logic network is then mapped to the actual technology
25 * using e.g. the "abc" pass.
26 *
27 * Note that this library does not map $mem cells. They must be mapped to logic
28 * and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
29 * which is of course highly recommended for larger memories.)
30 *
31 */
32
33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
35
36
37 // --------------------------------------------------------
38 // Use simplemap for trivial cell types
39 // --------------------------------------------------------
40
41 (* techmap_simplemap *)
42 (* techmap_celltype = "$pos $bu0" *)
43 module simplemap_buffers;
44 endmodule
45
46 (* techmap_simplemap *)
47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
48 module simplemap_bool_ops;
49 endmodule
50
51 (* techmap_simplemap *)
52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
53 module simplemap_reduce_ops;
54 endmodule
55
56 (* techmap_simplemap *)
57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
58 module simplemap_logic_ops;
59 endmodule
60
61 (* techmap_simplemap *)
62 (* techmap_celltype = "$slice $concat $mux" *)
63 module simplemap_various;
64 endmodule
65
66 (* techmap_simplemap *)
67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
68 module simplemap_registers;
69 endmodule
70
71
72 // --------------------------------------------------------
73 // Trivial substitutions
74 // --------------------------------------------------------
75
76 module \$neg (A, Y);
77 parameter A_SIGNED = 0;
78 parameter A_WIDTH = 1;
79 parameter Y_WIDTH = 1;
80
81 input [A_WIDTH-1:0] A;
82 output [Y_WIDTH-1:0] Y;
83
84 \$sub #(
85 .A_SIGNED(A_SIGNED),
86 .B_SIGNED(A_SIGNED),
87 .A_WIDTH(1),
88 .B_WIDTH(A_WIDTH),
89 .Y_WIDTH(Y_WIDTH)
90 ) _TECHMAP_REPLACE_ (
91 .A(1'b0),
92 .B(A),
93 .Y(Y)
94 );
95 endmodule
96
97 module \$ge (A, B, Y);
98 parameter A_SIGNED = 0;
99 parameter B_SIGNED = 0;
100 parameter A_WIDTH = 1;
101 parameter B_WIDTH = 1;
102 parameter Y_WIDTH = 1;
103
104 input [A_WIDTH-1:0] A;
105 input [B_WIDTH-1:0] B;
106 output [Y_WIDTH-1:0] Y;
107
108 \$le #(
109 .A_SIGNED(B_SIGNED),
110 .B_SIGNED(A_SIGNED),
111 .A_WIDTH(B_WIDTH),
112 .B_WIDTH(A_WIDTH),
113 .Y_WIDTH(Y_WIDTH)
114 ) _TECHMAP_REPLACE_ (
115 .A(B),
116 .B(A),
117 .Y(Y)
118 );
119 endmodule
120
121 module \$gt (A, B, Y);
122 parameter A_SIGNED = 0;
123 parameter B_SIGNED = 0;
124 parameter A_WIDTH = 1;
125 parameter B_WIDTH = 1;
126 parameter Y_WIDTH = 1;
127
128 input [A_WIDTH-1:0] A;
129 input [B_WIDTH-1:0] B;
130 output [Y_WIDTH-1:0] Y;
131
132 \$lt #(
133 .A_SIGNED(B_SIGNED),
134 .B_SIGNED(A_SIGNED),
135 .A_WIDTH(B_WIDTH),
136 .B_WIDTH(A_WIDTH),
137 .Y_WIDTH(Y_WIDTH)
138 ) _TECHMAP_REPLACE_ (
139 .A(B),
140 .B(A),
141 .Y(Y)
142 );
143 endmodule
144
145
146 // --------------------------------------------------------
147 // Shift operators
148 // --------------------------------------------------------
149
150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
152 parameter A_SIGNED = 0;
153 parameter B_SIGNED = 0;
154 parameter A_WIDTH = 1;
155 parameter B_WIDTH = 1;
156 parameter Y_WIDTH = 1;
157
158 parameter _TECHMAP_CELLTYPE_ = "";
159 localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
160 localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
161
162 input [A_WIDTH-1:0] A;
163 input [B_WIDTH-1:0] B;
164 output [Y_WIDTH-1:0] Y;
165
166 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
167 localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
168
169 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
170 wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
171
172 integer i;
173 reg [WIDTH-1:0] buffer;
174 reg overflow;
175
176 always @* begin
177 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
178 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
179
180 for (i = 0; i < BB_WIDTH; i = i+1)
181 if (B[i]) begin
182 if (shift_left)
183 buffer = {buffer, (2**i)'b0};
184 else if (2**i < WIDTH)
185 buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
186 else
187 buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
188 end
189 end
190
191 assign Y = buffer;
192 endmodule
193
194 (* techmap_celltype = "$shift $shiftx" *)
195 module shift_shiftx (A, B, Y);
196 parameter A_SIGNED = 0;
197 parameter B_SIGNED = 0;
198 parameter A_WIDTH = 1;
199 parameter B_WIDTH = 1;
200 parameter Y_WIDTH = 1;
201
202 input [A_WIDTH-1:0] A;
203 input [B_WIDTH-1:0] B;
204 output [Y_WIDTH-1:0] Y;
205
206 localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
207 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
208
209 parameter _TECHMAP_CELLTYPE_ = "";
210 localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
211
212 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
213 wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
214
215 integer i;
216 reg [WIDTH-1:0] buffer;
217 reg overflow;
218
219 always @* begin
220 overflow = 0;
221 buffer = {WIDTH{extbit}};
222 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
223
224 if (B_WIDTH > BB_WIDTH) begin
225 if (B_SIGNED) begin
226 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
227 if (B[i] != B[BB_WIDTH-1])
228 overflow = 1;
229 end else
230 overflow = |B[B_WIDTH-1:BB_WIDTH];
231 if (overflow)
232 buffer = {WIDTH{extbit}};
233 end
234
235 for (i = BB_WIDTH-1; i >= 0; i = i-1)
236 if (B[i]) begin
237 if (B_SIGNED && i == BB_WIDTH-1)
238 buffer = {buffer, {2**i{extbit}}};
239 else if (2**i < WIDTH)
240 buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
241 else
242 buffer = {WIDTH{extbit}};
243 end
244 end
245
246 assign Y = buffer;
247 endmodule
248
249
250 // --------------------------------------------------------
251 // ALU Infrastructure
252 // --------------------------------------------------------
253
254 module \$__alu_ripple (A, B, CI, X, Y, CO);
255 parameter WIDTH = 1;
256
257 input [WIDTH-1:0] A, B;
258 output [WIDTH-1:0] X, Y;
259
260 input CI;
261 output [WIDTH-1:0] CO;
262
263 wire [WIDTH:0] carry;
264 assign carry[0] = CI;
265 assign CO = carry[WIDTH:1];
266
267 genvar i;
268 generate
269 for (i = 0; i < WIDTH; i = i+1)
270 begin:V
271 // {x, y} = a + b + c
272 wire a, b, c, x, y;
273 wire t1, t2, t3;
274
275 \$_AND_ gate1 ( .A(a), .B(b), .Y(t1) );
276 \$_XOR_ gate2 ( .A(a), .B(b), .Y(t2) );
277 \$_AND_ gate3 ( .A(t2), .B(c), .Y(t3) );
278 \$_XOR_ gate4 ( .A(t2), .B(c), .Y(y) );
279 \$_OR_ gate5 ( .A(t1), .B(t3), .Y(x) );
280
281 assign a = A[i], b = B[i], c = carry[i];
282 assign carry[i+1] = x, X[i] = t2, Y[i] = y;
283 end
284 endgenerate
285 endmodule
286
287 module \$__lcu (P, G, CI, CO);
288 parameter WIDTH = 2;
289
290 input [WIDTH-1:0] P, G;
291 input CI;
292
293 output [WIDTH-1:0] CO;
294
295 integer i, j;
296 reg [WIDTH-1:0] p, g;
297
298 wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
299
300 always @* begin
301 p = P;
302 g = G;
303
304 // in almost all cases CI will be constant zero
305 g[0] = g[0] | (p[0] & CI);
306
307 // [[CITE]] Brent Kung Adder
308 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
309 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
310
311 // Main tree
312 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
313 for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
314 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
315 p[j] = p[j] & p[j - 2**(i-1)];
316 end
317 end
318
319 // Inverse tree
320 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
321 for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
322 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
323 p[j] = p[j] & p[j - 2**(i-1)];
324 end
325 end
326 end
327
328 assign CO = g;
329 endmodule
330
331 module \$__alu_lookahead (A, B, CI, X, Y, CO);
332 parameter WIDTH = 1;
333
334 input [WIDTH-1:0] A, B;
335 output [WIDTH-1:0] X, Y;
336
337 input CI;
338 output [WIDTH-1:0] CO;
339
340 wire [WIDTH-1:0] P, G;
341 wire [WIDTH:0] carry;
342
343 genvar i;
344 generate
345 for (i = 0; i < WIDTH; i = i+1)
346 begin:V
347 wire a, b, c, p, g, y;
348
349 \$_AND_ gate1 ( .A(a), .B(b), .Y(g) );
350 \$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
351 \$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
352
353 assign a = A[i], b = B[i], c = carry[i];
354 assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
355 end
356 endgenerate
357
358 \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
359 assign carry = {CO, CI};
360 endmodule
361
362 module \$alu (A, B, CI, BI, X, Y, CO);
363 parameter A_SIGNED = 0;
364 parameter B_SIGNED = 0;
365 parameter A_WIDTH = 1;
366 parameter B_WIDTH = 1;
367 parameter Y_WIDTH = 1;
368
369 input [A_WIDTH-1:0] A;
370 input [B_WIDTH-1:0] B;
371 output [Y_WIDTH-1:0] X, Y;
372
373 input CI, BI;
374 output [Y_WIDTH-1:0] CO;
375
376 wire [Y_WIDTH-1:0] A_buf, B_buf;
377 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
378 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
379
380 `ifdef ALU_RIPPLE
381 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
382 `else
383 if (Y_WIDTH <= 4) begin
384 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
385 end else begin
386 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
387 end
388 `endif
389 endmodule
390
391
392 // --------------------------------------------------------
393 // ALU Cell Types: Compare, Add, Subtract
394 // --------------------------------------------------------
395
396 `define ALU_COMMONS(_width, _sub) """
397 parameter A_SIGNED = 0;
398 parameter B_SIGNED = 0;
399 parameter A_WIDTH = 1;
400 parameter B_WIDTH = 1;
401 parameter Y_WIDTH = 1;
402
403 localparam WIDTH = _width;
404
405 input [A_WIDTH-1:0] A;
406 input [B_WIDTH-1:0] B;
407 output [Y_WIDTH-1:0] Y;
408
409 wire [WIDTH-1:0] alu_x, alu_y, alu_co;
410 wire [WIDTH:0] carry = {alu_co, |_sub};
411
412 \$alu #(
413 .A_SIGNED(A_SIGNED),
414 .B_SIGNED(B_SIGNED),
415 .A_WIDTH(A_WIDTH),
416 .B_WIDTH(B_WIDTH),
417 .Y_WIDTH(WIDTH)
418 ) alu (
419 .A(A),
420 .B(B),
421 .CI(|_sub),
422 .BI(|_sub),
423 .X(alu_x),
424 .Y(alu_y),
425 .CO(alu_co)
426 );
427
428 wire cf, of, zf, sf;
429 assign cf = !carry[WIDTH];
430 assign of = carry[WIDTH] ^ carry[WIDTH-1];
431 assign sf = alu_y[WIDTH-1];
432 """
433
434 module \$lt (A, B, Y);
435 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
436 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
437 assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
438 endmodule
439
440 module \$le (A, B, Y);
441 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
442 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
443 assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
444 endmodule
445
446 module \$add (A, B, Y);
447 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
448 `ALU_COMMONS(Y_WIDTH, 0)
449 assign Y = alu_y;
450 endmodule
451
452 module \$sub (A, B, Y);
453 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
454 `ALU_COMMONS(Y_WIDTH, 1)
455 assign Y = alu_y;
456 endmodule
457
458
459 // --------------------------------------------------------
460 // Multiply
461 // --------------------------------------------------------
462
463 module \$__acc_set (acc_new, value);
464 parameter WIDTH = 1;
465 output reg [2*WIDTH-1:0] acc_new;
466 input [WIDTH-1:0] value;
467
468 wire [1023:0] _TECHMAP_DO_ = "proc;;;";
469
470 integer k;
471 always @* begin
472 for (k = 0; k < WIDTH; k = k+1) begin
473 acc_new[2*k +: 2] = value[k];
474 end
475 end
476 endmodule
477
478 module \$__acc_add (acc_new, acc_old, value);
479 parameter WIDTH = 1;
480 output reg [2*WIDTH-1:0] acc_new;
481 input [2*WIDTH-1:0] acc_old;
482 input [WIDTH-1:0] value;
483
484 wire [1023:0] _TECHMAP_DO_ = "proc; simplemap; opt -purge";
485
486 integer k;
487 reg a, b, c;
488
489 always @* begin
490 for (k = 0; k < WIDTH; k = k+1) begin
491 a = acc_old[2*k];
492 b = k ? acc_old[2*k-1] : 1'b0;
493 c = value[k];
494 acc_new[2*k] = (a ^ b) ^ c;
495 acc_new[2*k+1] = (a & b) | ((a ^ b) & c);
496 end
497 end
498 endmodule
499
500 module \$__acc_get (value, acc);
501 parameter WIDTH = 1;
502 output reg [WIDTH-1:0] value;
503 input [2*WIDTH-1:0] acc;
504
505 wire [1023:0] _TECHMAP_DO_ = "proc;;;";
506
507 integer k;
508
509 always @* begin
510 // at the end of the multiplier chain the carry-save accumulator
511 // should also have propagated all carries. thus we just need to
512 // copy the even bits from the carry accumulator to the output.
513 for (k = 0; k < WIDTH; k = k+1) begin
514 value[k] = acc[2*k];
515 end
516 end
517 endmodule
518
519 module \$__acc_mul (A, B, Y);
520 parameter WIDTH = 1;
521 input [WIDTH-1:0] A, B;
522 output [WIDTH-1:0] Y;
523
524 wire [1023:0] _TECHMAP_DO_ = "proc;;";
525
526 integer i;
527 reg [WIDTH-1:0] x;
528 reg [2*WIDTH-1:0] y;
529
530 (* via_celltype = "\\$__acc_set acc_new" *)
531 (* via_celltype_defparam_WIDTH = WIDTH *)
532 function [2*WIDTH-1:0] acc_set;
533 input [WIDTH-1:0] value;
534 endfunction
535
536 (* via_celltype = "\\$__acc_add acc_new" *)
537 (* via_celltype_defparam_WIDTH = WIDTH *)
538 function [2*WIDTH-1:0] acc_add;
539 input [2*WIDTH-1:0] acc_old;
540 input [WIDTH-1:0] value;
541 endfunction
542
543 (* via_celltype = "\\$__acc_get value" *)
544 (* via_celltype_defparam_WIDTH = WIDTH *)
545 function [WIDTH-1:0] acc_get;
546 input [2*WIDTH-1:0] acc;
547 endfunction
548
549 always @* begin
550 x = B;
551 y = acc_set(A[0] ? x : 1'b0);
552 for (i = 1; i < WIDTH; i = i+1) begin
553 x = {x[WIDTH-2:0], 1'b0};
554 y = acc_add(y, A[i] ? x : 1'b0);
555 end
556 end
557
558 assign Y = acc_get(y);
559 endmodule
560
561 module \$mul (A, B, Y);
562 parameter A_SIGNED = 0;
563 parameter B_SIGNED = 0;
564 parameter A_WIDTH = 1;
565 parameter B_WIDTH = 1;
566 parameter Y_WIDTH = 1;
567
568 input [A_WIDTH-1:0] A;
569 input [B_WIDTH-1:0] B;
570 output [Y_WIDTH-1:0] Y;
571
572 wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
573
574 wire [Y_WIDTH-1:0] A_buf, B_buf;
575 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
576 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
577
578 \$__acc_mul #(
579 .WIDTH(Y_WIDTH)
580 ) _TECHMAP_REPLACE_ (
581 .A(A_buf),
582 .B(B_buf),
583 .Y(Y)
584 );
585 endmodule
586
587
588 // --------------------------------------------------------
589 // Divide and Modulo
590 // --------------------------------------------------------
591
592 module \$__div_mod_u (A, B, Y, R);
593 parameter WIDTH = 1;
594
595 input [WIDTH-1:0] A, B;
596 output [WIDTH-1:0] Y, R;
597
598 wire [WIDTH*WIDTH-1:0] chaindata;
599 assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
600
601 genvar i;
602 generate begin
603 for (i = 0; i < WIDTH; i=i+1) begin:stage
604 wire [WIDTH-1:0] stage_in;
605
606 if (i == 0) begin:cp
607 assign stage_in = A;
608 end else begin:cp
609 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
610 end
611
612 assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
613 assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
614 end
615 end endgenerate
616 endmodule
617
618 module \$__div_mod (A, B, Y, R);
619 parameter A_SIGNED = 0;
620 parameter B_SIGNED = 0;
621 parameter A_WIDTH = 1;
622 parameter B_WIDTH = 1;
623 parameter Y_WIDTH = 1;
624
625 localparam WIDTH =
626 A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
627 B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
628
629 input [A_WIDTH-1:0] A;
630 input [B_WIDTH-1:0] B;
631 output [Y_WIDTH-1:0] Y, R;
632
633 wire [WIDTH-1:0] A_buf, B_buf;
634 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
635 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
636
637 wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
638 assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
639 assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
640
641 \$__div_mod_u #(
642 .WIDTH(WIDTH)
643 ) div_mod_u (
644 .A(A_buf_u),
645 .B(B_buf_u),
646 .Y(Y_u),
647 .R(R_u)
648 );
649
650 assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
651 assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
652 endmodule
653
654 module \$div (A, B, Y);
655 parameter A_SIGNED = 0;
656 parameter B_SIGNED = 0;
657 parameter A_WIDTH = 1;
658 parameter B_WIDTH = 1;
659 parameter Y_WIDTH = 1;
660
661 input [A_WIDTH-1:0] A;
662 input [B_WIDTH-1:0] B;
663 output [Y_WIDTH-1:0] Y;
664
665 \$__div_mod #(
666 .A_SIGNED(A_SIGNED),
667 .B_SIGNED(B_SIGNED),
668 .A_WIDTH(A_WIDTH),
669 .B_WIDTH(B_WIDTH),
670 .Y_WIDTH(Y_WIDTH)
671 ) div_mod (
672 .A(A),
673 .B(B),
674 .Y(Y)
675 );
676 endmodule
677
678 module \$mod (A, B, Y);
679 parameter A_SIGNED = 0;
680 parameter B_SIGNED = 0;
681 parameter A_WIDTH = 1;
682 parameter B_WIDTH = 1;
683 parameter Y_WIDTH = 1;
684
685 input [A_WIDTH-1:0] A;
686 input [B_WIDTH-1:0] B;
687 output [Y_WIDTH-1:0] Y;
688
689 \$__div_mod #(
690 .A_SIGNED(A_SIGNED),
691 .B_SIGNED(B_SIGNED),
692 .A_WIDTH(A_WIDTH),
693 .B_WIDTH(B_WIDTH),
694 .Y_WIDTH(Y_WIDTH)
695 ) div_mod (
696 .A(A),
697 .B(B),
698 .R(Y)
699 );
700 endmodule
701
702
703 // --------------------------------------------------------
704 // Power
705 // --------------------------------------------------------
706
707 module \$pow (A, B, Y);
708 parameter A_SIGNED = 0;
709 parameter B_SIGNED = 0;
710 parameter A_WIDTH = 1;
711 parameter B_WIDTH = 1;
712 parameter Y_WIDTH = 1;
713
714 input [A_WIDTH-1:0] A;
715 input [B_WIDTH-1:0] B;
716 output [Y_WIDTH-1:0] Y;
717
718 wire _TECHMAP_FAIL_ = 1;
719 endmodule
720
721
722 // --------------------------------------------------------
723 // Equal and Not-Equal
724 // --------------------------------------------------------
725
726 module \$eq (A, B, Y);
727 parameter A_SIGNED = 0;
728 parameter B_SIGNED = 0;
729 parameter A_WIDTH = 1;
730 parameter B_WIDTH = 1;
731 parameter Y_WIDTH = 1;
732
733 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
734
735 input [A_WIDTH-1:0] A;
736 input [B_WIDTH-1:0] B;
737 output [Y_WIDTH-1:0] Y;
738
739 wire carry, carry_sign;
740 wire [WIDTH-1:0] A_buf, B_buf;
741 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
742 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
743
744 assign Y = ~|(A_buf ^ B_buf);
745 endmodule
746
747 module \$ne (A, B, Y);
748 parameter A_SIGNED = 0;
749 parameter B_SIGNED = 0;
750 parameter A_WIDTH = 1;
751 parameter B_WIDTH = 1;
752 parameter Y_WIDTH = 1;
753
754 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
755
756 input [A_WIDTH-1:0] A;
757 input [B_WIDTH-1:0] B;
758 output [Y_WIDTH-1:0] Y;
759
760 wire carry, carry_sign;
761 wire [WIDTH-1:0] A_buf, B_buf;
762 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
763 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
764
765 assign Y = |(A_buf ^ B_buf);
766 endmodule
767
768 module \$eqx (A, B, Y);
769 parameter A_SIGNED = 0;
770 parameter B_SIGNED = 0;
771 parameter A_WIDTH = 1;
772 parameter B_WIDTH = 1;
773 parameter Y_WIDTH = 1;
774
775 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
776
777 input [A_WIDTH-1:0] A;
778 input [B_WIDTH-1:0] B;
779 output [Y_WIDTH-1:0] Y;
780
781 wire carry, carry_sign;
782 wire [WIDTH-1:0] A_buf, B_buf;
783 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
784 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
785
786 assign Y = ~|(A_buf ^ B_buf);
787 endmodule
788
789 module \$nex (A, B, Y);
790 parameter A_SIGNED = 0;
791 parameter B_SIGNED = 0;
792 parameter A_WIDTH = 1;
793 parameter B_WIDTH = 1;
794 parameter Y_WIDTH = 1;
795
796 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
797
798 input [A_WIDTH-1:0] A;
799 input [B_WIDTH-1:0] B;
800 output [Y_WIDTH-1:0] Y;
801
802 wire carry, carry_sign;
803 wire [WIDTH-1:0] A_buf, B_buf;
804 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
805 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
806
807 assign Y = |(A_buf ^ B_buf);
808 endmodule
809
810
811 // --------------------------------------------------------
812 // Parallel Multiplexers
813 // --------------------------------------------------------
814
815 module \$pmux (A, B, S, Y);
816 parameter WIDTH = 1;
817 parameter S_WIDTH = 1;
818
819 input [WIDTH-1:0] A;
820 input [WIDTH*S_WIDTH-1:0] B;
821 input [S_WIDTH-1:0] S;
822 output [WIDTH-1:0] Y;
823
824 wire [WIDTH-1:0] Y_B;
825
826 genvar i, j;
827 generate
828 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
829 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
830 assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
831 end:B_AND
832 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
833 wire [S_WIDTH-1:0] B_AND_BITS;
834 for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
835 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
836 end:B_AND_BITS_COLLECT
837 assign Y_B[i] = |B_AND_BITS;
838 end:B_OR
839 endgenerate
840
841 assign Y = |S ? Y_B : A;
842 endmodule
843