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Replaced recursive lcu scheme with bk adder
[yosys.git] / techlibs / common / techmap.v
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The internal logic cell technology mapper.
21 *
22 * This verilog library contains the mapping of internal cells (e.g. $not with
23 * variable bit width) to the internal logic cells (such as the single bit $_NOT_
24 * gate). Usually this logic network is then mapped to the actual technology
25 * using e.g. the "abc" pass.
26 *
27 * Note that this library does not map $mem cells. They must be mapped to logic
28 * and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
29 * which is of course highly recommended for larger memories.)
30 *
31 */
32
33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
35
36
37 // --------------------------------------------------------
38 // Use simplemap for trivial cell types
39 // --------------------------------------------------------
40
41 (* techmap_simplemap *)
42 (* techmap_celltype = "$pos $bu0" *)
43 module simplemap_buffers;
44 endmodule
45
46 (* techmap_simplemap *)
47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
48 module simplemap_bool_ops;
49 endmodule
50
51 (* techmap_simplemap *)
52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
53 module simplemap_reduce_ops;
54 endmodule
55
56 (* techmap_simplemap *)
57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
58 module simplemap_logic_ops;
59 endmodule
60
61 (* techmap_simplemap *)
62 (* techmap_celltype = "$slice $concat $mux" *)
63 module simplemap_various;
64 endmodule
65
66 (* techmap_simplemap *)
67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
68 module simplemap_registers;
69 endmodule
70
71
72 // --------------------------------------------------------
73 // Trivial substitutions
74 // --------------------------------------------------------
75
76 module \$neg (A, Y);
77 parameter A_SIGNED = 0;
78 parameter A_WIDTH = 1;
79 parameter Y_WIDTH = 1;
80
81 input [A_WIDTH-1:0] A;
82 output [Y_WIDTH-1:0] Y;
83
84 \$sub #(
85 .A_SIGNED(A_SIGNED),
86 .B_SIGNED(A_SIGNED),
87 .A_WIDTH(1),
88 .B_WIDTH(A_WIDTH),
89 .Y_WIDTH(Y_WIDTH)
90 ) _TECHMAP_REPLACE_ (
91 .A(1'b0),
92 .B(A),
93 .Y(Y)
94 );
95 endmodule
96
97 module \$ge (A, B, Y);
98 parameter A_SIGNED = 0;
99 parameter B_SIGNED = 0;
100 parameter A_WIDTH = 1;
101 parameter B_WIDTH = 1;
102 parameter Y_WIDTH = 1;
103
104 input [A_WIDTH-1:0] A;
105 input [B_WIDTH-1:0] B;
106 output [Y_WIDTH-1:0] Y;
107
108 \$le #(
109 .A_SIGNED(B_SIGNED),
110 .B_SIGNED(A_SIGNED),
111 .A_WIDTH(B_WIDTH),
112 .B_WIDTH(A_WIDTH),
113 .Y_WIDTH(Y_WIDTH)
114 ) _TECHMAP_REPLACE_ (
115 .A(B),
116 .B(A),
117 .Y(Y)
118 );
119 endmodule
120
121 module \$gt (A, B, Y);
122 parameter A_SIGNED = 0;
123 parameter B_SIGNED = 0;
124 parameter A_WIDTH = 1;
125 parameter B_WIDTH = 1;
126 parameter Y_WIDTH = 1;
127
128 input [A_WIDTH-1:0] A;
129 input [B_WIDTH-1:0] B;
130 output [Y_WIDTH-1:0] Y;
131
132 \$lt #(
133 .A_SIGNED(B_SIGNED),
134 .B_SIGNED(A_SIGNED),
135 .A_WIDTH(B_WIDTH),
136 .B_WIDTH(A_WIDTH),
137 .Y_WIDTH(Y_WIDTH)
138 ) _TECHMAP_REPLACE_ (
139 .A(B),
140 .B(A),
141 .Y(Y)
142 );
143 endmodule
144
145
146 // --------------------------------------------------------
147 // Shift operators
148 // --------------------------------------------------------
149
150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
152 parameter A_SIGNED = 0;
153 parameter B_SIGNED = 0;
154 parameter A_WIDTH = 1;
155 parameter B_WIDTH = 1;
156 parameter Y_WIDTH = 1;
157
158 parameter _TECHMAP_CELLTYPE_ = "";
159 localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
160 localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
161
162 input [A_WIDTH-1:0] A;
163 input [B_WIDTH-1:0] B;
164 output [Y_WIDTH-1:0] Y;
165
166 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
167 localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
168
169 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
170 wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
171
172 integer i;
173 reg [WIDTH-1:0] buffer;
174 reg overflow;
175
176 always @* begin
177 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
178 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
179
180 for (i = 0; i < BB_WIDTH; i = i+1)
181 if (B[i]) begin
182 if (shift_left)
183 buffer = {buffer, (2**i)'b0};
184 else if (2**i < WIDTH)
185 buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
186 else
187 buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
188 end
189 end
190
191 assign Y = buffer;
192 endmodule
193
194 (* techmap_celltype = "$shift $shiftx" *)
195 module shift_shiftx (A, B, Y);
196 parameter A_SIGNED = 0;
197 parameter B_SIGNED = 0;
198 parameter A_WIDTH = 1;
199 parameter B_WIDTH = 1;
200 parameter Y_WIDTH = 1;
201
202 input [A_WIDTH-1:0] A;
203 input [B_WIDTH-1:0] B;
204 output [Y_WIDTH-1:0] Y;
205
206 localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
207 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
208
209 parameter _TECHMAP_CELLTYPE_ = "";
210 localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
211
212 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
213 wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
214
215 integer i;
216 reg [WIDTH-1:0] buffer;
217 reg overflow;
218
219 always @* begin
220 overflow = 0;
221 buffer = {WIDTH{extbit}};
222 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
223
224 if (B_WIDTH > BB_WIDTH) begin
225 if (B_SIGNED) begin
226 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
227 if (B[i] != B[BB_WIDTH-1])
228 overflow = 1;
229 end else
230 overflow = |B[B_WIDTH-1:BB_WIDTH];
231 if (overflow)
232 buffer = {WIDTH{extbit}};
233 end
234
235 for (i = BB_WIDTH-1; i >= 0; i = i-1)
236 if (B[i]) begin
237 if (B_SIGNED && i == BB_WIDTH-1)
238 buffer = {buffer, {2**i{extbit}}};
239 else if (2**i < WIDTH)
240 buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
241 else
242 buffer = {WIDTH{extbit}};
243 end
244 end
245
246 assign Y = buffer;
247 endmodule
248
249
250 // --------------------------------------------------------
251 // ALU Infrastructure
252 // --------------------------------------------------------
253
254 module \$__alu_ripple (A, B, CI, X, Y, CO, CS);
255 parameter WIDTH = 1;
256
257 input [WIDTH-1:0] A, B;
258 output [WIDTH-1:0] X, Y;
259
260 input CI;
261 output CO, CS;
262
263 wire [WIDTH:0] carry;
264 assign carry[0] = CI;
265 assign CO = carry[WIDTH];
266 assign CS = carry[WIDTH-1];
267
268 genvar i;
269 generate
270 for (i = 0; i < WIDTH; i = i+1)
271 begin:V
272 // {x, y} = a + b + c
273 wire a, b, c, x, y;
274 wire t1, t2, t3;
275
276 \$_AND_ gate1 ( .A(a), .B(b), .Y(t1) );
277 \$_XOR_ gate2 ( .A(a), .B(b), .Y(t2) );
278 \$_AND_ gate3 ( .A(t2), .B(c), .Y(t3) );
279 \$_XOR_ gate4 ( .A(t2), .B(c), .Y(y) );
280 \$_OR_ gate5 ( .A(t1), .B(t3), .Y(x) );
281
282 assign a = A[i], b = B[i], c = carry[i];
283 assign carry[i+1] = x, X[i] = t2, Y[i] = y;
284 end
285 endgenerate
286 endmodule
287
288 module \$__lcu (P, G, CI, CO);
289 parameter WIDTH = 2;
290
291 input [WIDTH-1:0] P, G;
292 input CI;
293
294 output reg [WIDTH:0] CO;
295
296 integer i, j, k;
297 reg [WIDTH-1:0] p, g;
298
299 wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
300
301 always @* begin
302 p = P;
303 g = G;
304
305 // in almost all cases CI will be constant zero
306 g[0] = g[0] | (p[0] & CI);
307
308 // [[CITE]] Brent Kung Adder
309 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
310 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
311
312 // Main tree
313 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
314 for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
315 k = j - 2**(i-1);
316 g[j] = g[j] | p[j] & g[k];
317 p[j] = p[j] & p[k];
318 end
319 end
320
321 // Inverse tree
322 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
323 for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
324 k = j - 2**(i-1);
325 g[j] = g[j] | p[j] & g[k];
326 p[j] = p[j] & p[k];
327 end
328 end
329 end
330
331 assign CO = {g, CI};
332 endmodule
333
334 module \$__alu_lookahead (A, B, CI, X, Y, CO, CS);
335 parameter WIDTH = 1;
336
337 input [WIDTH-1:0] A, B;
338 output [WIDTH-1:0] X, Y;
339
340 input CI;
341 output CO, CS;
342
343 wire [WIDTH-1:0] P, G;
344 wire [WIDTH:0] C;
345
346 assign CO = C[WIDTH];
347 assign CS = C[WIDTH-1];
348
349 genvar i;
350 generate
351 for (i = 0; i < WIDTH; i = i+1)
352 begin:V
353 wire a, b, c, p, g, y;
354
355 \$_AND_ gate1 ( .A(a), .B(b), .Y(g) );
356 \$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
357 \$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
358
359 assign a = A[i], b = B[i], c = C[i];
360 assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
361 end
362 endgenerate
363
364 \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
365 endmodule
366
367 module \$__alu (A, B, CI, BI, X, Y, CO, CS);
368 parameter A_SIGNED = 0;
369 parameter B_SIGNED = 0;
370 parameter A_WIDTH = 1;
371 parameter B_WIDTH = 1;
372 parameter Y_WIDTH = 1;
373
374 input [A_WIDTH-1:0] A;
375 input [B_WIDTH-1:0] B;
376 output [Y_WIDTH-1:0] X, Y;
377
378 // carry in, sub, carry out, carry sign
379 input CI, BI;
380 output CO, CS;
381
382 wire [Y_WIDTH-1:0] A_buf, B_buf;
383 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
384 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
385
386 `ifdef ALU_RIPPLE
387 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
388 `else
389 if (Y_WIDTH <= 4) begin
390 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
391 end else begin
392 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
393 end
394 `endif
395 endmodule
396
397
398 // --------------------------------------------------------
399 // ALU Cell Types: Compare, Add, Subtract
400 // --------------------------------------------------------
401
402 `define ALU_COMMONS(_width, _ci, _bi) """
403 parameter A_SIGNED = 0;
404 parameter B_SIGNED = 0;
405 parameter A_WIDTH = 1;
406 parameter B_WIDTH = 1;
407 parameter Y_WIDTH = 1;
408
409 localparam WIDTH = _width;
410
411 input [A_WIDTH-1:0] A;
412 input [B_WIDTH-1:0] B;
413 output [Y_WIDTH-1:0] Y;
414
415 wire alu_co, alu_cs;
416 wire [WIDTH-1:0] alu_x, alu_y;
417
418 \$__alu #(
419 .A_SIGNED(A_SIGNED),
420 .B_SIGNED(B_SIGNED),
421 .A_WIDTH(A_WIDTH),
422 .B_WIDTH(B_WIDTH),
423 .Y_WIDTH(WIDTH)
424 ) alu (
425 .A(A),
426 .B(B),
427 .CI(_ci),
428 .BI(_bi),
429 .X(alu_x),
430 .Y(alu_y),
431 .CO(alu_co),
432 .CS(alu_cs)
433 );
434
435 wire cf, of, zf, sf;
436 assign cf = !alu_co;
437 assign of = alu_co ^ alu_cs;
438 assign sf = alu_y[WIDTH-1];
439 """
440
441 module \$lt (A, B, Y);
442 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
443 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
444 assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
445 endmodule
446
447 module \$le (A, B, Y);
448 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
449 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
450 assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
451 endmodule
452
453 module \$add (A, B, Y);
454 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
455 `ALU_COMMONS(Y_WIDTH, 0, 0)
456 assign Y = alu_y;
457 endmodule
458
459 module \$sub (A, B, Y);
460 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
461 `ALU_COMMONS(Y_WIDTH, 1, 1)
462 assign Y = alu_y;
463 endmodule
464
465
466 // --------------------------------------------------------
467 // Multiply
468 // --------------------------------------------------------
469
470 module \$__arraymul (A, B, Y);
471 parameter WIDTH = 8;
472 input [WIDTH-1:0] A, B;
473 output [WIDTH-1:0] Y;
474
475 wire [1023:0] _TECHMAP_DO_ = "proc;; opt";
476
477 integer i;
478 reg [WIDTH-1:0] x;
479 reg [2*WIDTH-1:0] y;
480
481 function [2*WIDTH-1:0] acc_set;
482 input [WIDTH-1:0] value;
483 integer k;
484 begin
485 for (k = 0; k < WIDTH; k = k+1) begin
486 acc_set[2*k +: 2] = value[k];
487 end
488 end
489 endfunction
490
491 function [2*WIDTH-1:0] acc_add;
492 input [2*WIDTH-1:0] old_acc;
493 input [WIDTH-1:0] value;
494 integer k;
495 reg a, b, c;
496 begin
497 for (k = 0; k < WIDTH; k = k+1) begin
498 a = old_acc[2*k];
499 b = k ? old_acc[2*k-1] : 1'b0;
500 c = value[k];
501 acc_add[2*k] = (a ^ b) ^ c;
502 acc_add[2*k+1] = (a & b) | ((a ^ b) & c);
503 end
504 end
505 endfunction
506
507 function [WIDTH-1:0] acc_get;
508 input [2*WIDTH-1:0] acc;
509 integer k;
510 begin
511 // at the end of the multiplier chain the carry-save accumulator
512 // should also have propagated all carries. thus we just need to
513 // copy the even bits from the carry accumulator to the output.
514 for (k = 0; k < WIDTH; k = k+1) begin
515 acc_get[k] = acc[2*k];
516 end
517 end
518 endfunction
519
520 always @* begin
521 x = B;
522 y = acc_set(A[0] ? x : 0);
523 for (i = 1; i < WIDTH; i = i+1) begin
524 x = {x[WIDTH-2:0], 1'b0};
525 y = acc_add(y, A[i] ? x : 0);
526 end
527 end
528
529 assign Y = acc_get(y);
530 endmodule
531
532 module \$mul (A, B, Y);
533 parameter A_SIGNED = 0;
534 parameter B_SIGNED = 0;
535 parameter A_WIDTH = 1;
536 parameter B_WIDTH = 1;
537 parameter Y_WIDTH = 1;
538
539 input [A_WIDTH-1:0] A;
540 input [B_WIDTH-1:0] B;
541 output [Y_WIDTH-1:0] Y;
542
543 wire [Y_WIDTH-1:0] A_buf, B_buf;
544 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
545 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
546
547 \$__arraymul #(
548 .WIDTH(Y_WIDTH)
549 ) arraymul (
550 .A(A_buf),
551 .B(B_buf),
552 .Y(Y)
553 );
554 endmodule
555
556
557 // --------------------------------------------------------
558 // Divide and Modulo
559 // --------------------------------------------------------
560
561 module \$__div_mod_u (A, B, Y, R);
562 parameter WIDTH = 1;
563
564 input [WIDTH-1:0] A, B;
565 output [WIDTH-1:0] Y, R;
566
567 wire [WIDTH*WIDTH-1:0] chaindata;
568 assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
569
570 genvar i;
571 generate begin
572 for (i = 0; i < WIDTH; i=i+1) begin:stage
573 wire [WIDTH-1:0] stage_in;
574
575 if (i == 0) begin:cp
576 assign stage_in = A;
577 end else begin:cp
578 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
579 end
580
581 assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
582 assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
583 end
584 end endgenerate
585 endmodule
586
587 module \$__div_mod (A, B, Y, R);
588 parameter A_SIGNED = 0;
589 parameter B_SIGNED = 0;
590 parameter A_WIDTH = 1;
591 parameter B_WIDTH = 1;
592 parameter Y_WIDTH = 1;
593
594 localparam WIDTH =
595 A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
596 B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
597
598 input [A_WIDTH-1:0] A;
599 input [B_WIDTH-1:0] B;
600 output [Y_WIDTH-1:0] Y, R;
601
602 wire [WIDTH-1:0] A_buf, B_buf;
603 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
604 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
605
606 wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
607 assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
608 assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
609
610 \$__div_mod_u #(
611 .WIDTH(WIDTH)
612 ) div_mod_u (
613 .A(A_buf_u),
614 .B(B_buf_u),
615 .Y(Y_u),
616 .R(R_u)
617 );
618
619 assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
620 assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
621 endmodule
622
623 module \$div (A, B, Y);
624 parameter A_SIGNED = 0;
625 parameter B_SIGNED = 0;
626 parameter A_WIDTH = 1;
627 parameter B_WIDTH = 1;
628 parameter Y_WIDTH = 1;
629
630 input [A_WIDTH-1:0] A;
631 input [B_WIDTH-1:0] B;
632 output [Y_WIDTH-1:0] Y;
633
634 \$__div_mod #(
635 .A_SIGNED(A_SIGNED),
636 .B_SIGNED(B_SIGNED),
637 .A_WIDTH(A_WIDTH),
638 .B_WIDTH(B_WIDTH),
639 .Y_WIDTH(Y_WIDTH)
640 ) div_mod (
641 .A(A),
642 .B(B),
643 .Y(Y)
644 );
645 endmodule
646
647 module \$mod (A, B, Y);
648 parameter A_SIGNED = 0;
649 parameter B_SIGNED = 0;
650 parameter A_WIDTH = 1;
651 parameter B_WIDTH = 1;
652 parameter Y_WIDTH = 1;
653
654 input [A_WIDTH-1:0] A;
655 input [B_WIDTH-1:0] B;
656 output [Y_WIDTH-1:0] Y;
657
658 \$__div_mod #(
659 .A_SIGNED(A_SIGNED),
660 .B_SIGNED(B_SIGNED),
661 .A_WIDTH(A_WIDTH),
662 .B_WIDTH(B_WIDTH),
663 .Y_WIDTH(Y_WIDTH)
664 ) div_mod (
665 .A(A),
666 .B(B),
667 .R(Y)
668 );
669 endmodule
670
671
672 // --------------------------------------------------------
673 // Power
674 // --------------------------------------------------------
675
676 module \$pow (A, B, Y);
677 parameter A_SIGNED = 0;
678 parameter B_SIGNED = 0;
679 parameter A_WIDTH = 1;
680 parameter B_WIDTH = 1;
681 parameter Y_WIDTH = 1;
682
683 input [A_WIDTH-1:0] A;
684 input [B_WIDTH-1:0] B;
685 output [Y_WIDTH-1:0] Y;
686
687 wire _TECHMAP_FAIL_ = 1;
688 endmodule
689
690
691 // --------------------------------------------------------
692 // Equal and Not-Equal
693 // --------------------------------------------------------
694
695 module \$eq (A, B, Y);
696 parameter A_SIGNED = 0;
697 parameter B_SIGNED = 0;
698 parameter A_WIDTH = 1;
699 parameter B_WIDTH = 1;
700 parameter Y_WIDTH = 1;
701
702 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
703
704 input [A_WIDTH-1:0] A;
705 input [B_WIDTH-1:0] B;
706 output [Y_WIDTH-1:0] Y;
707
708 wire carry, carry_sign;
709 wire [WIDTH-1:0] A_buf, B_buf;
710 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
711 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
712
713 assign Y = ~|(A_buf ^ B_buf);
714 endmodule
715
716 module \$ne (A, B, Y);
717 parameter A_SIGNED = 0;
718 parameter B_SIGNED = 0;
719 parameter A_WIDTH = 1;
720 parameter B_WIDTH = 1;
721 parameter Y_WIDTH = 1;
722
723 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
724
725 input [A_WIDTH-1:0] A;
726 input [B_WIDTH-1:0] B;
727 output [Y_WIDTH-1:0] Y;
728
729 wire carry, carry_sign;
730 wire [WIDTH-1:0] A_buf, B_buf;
731 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
732 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
733
734 assign Y = |(A_buf ^ B_buf);
735 endmodule
736
737 module \$eqx (A, B, Y);
738 parameter A_SIGNED = 0;
739 parameter B_SIGNED = 0;
740 parameter A_WIDTH = 1;
741 parameter B_WIDTH = 1;
742 parameter Y_WIDTH = 1;
743
744 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
745
746 input [A_WIDTH-1:0] A;
747 input [B_WIDTH-1:0] B;
748 output [Y_WIDTH-1:0] Y;
749
750 wire carry, carry_sign;
751 wire [WIDTH-1:0] A_buf, B_buf;
752 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
753 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
754
755 assign Y = ~|(A_buf ^ B_buf);
756 endmodule
757
758 module \$nex (A, B, Y);
759 parameter A_SIGNED = 0;
760 parameter B_SIGNED = 0;
761 parameter A_WIDTH = 1;
762 parameter B_WIDTH = 1;
763 parameter Y_WIDTH = 1;
764
765 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
766
767 input [A_WIDTH-1:0] A;
768 input [B_WIDTH-1:0] B;
769 output [Y_WIDTH-1:0] Y;
770
771 wire carry, carry_sign;
772 wire [WIDTH-1:0] A_buf, B_buf;
773 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
774 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
775
776 assign Y = |(A_buf ^ B_buf);
777 endmodule
778
779
780 // --------------------------------------------------------
781 // Parallel Multiplexers
782 // --------------------------------------------------------
783
784 module \$pmux (A, B, S, Y);
785 parameter WIDTH = 1;
786 parameter S_WIDTH = 1;
787
788 input [WIDTH-1:0] A;
789 input [WIDTH*S_WIDTH-1:0] B;
790 input [S_WIDTH-1:0] S;
791 output [WIDTH-1:0] Y;
792
793 wire [WIDTH-1:0] Y_B;
794
795 genvar i, j;
796 generate
797 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
798 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
799 assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
800 end:B_AND
801 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
802 wire [S_WIDTH-1:0] B_AND_BITS;
803 for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
804 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
805 end:B_AND_BITS_COLLECT
806 assign Y_B[i] = |B_AND_BITS;
807 end:B_OR
808 endgenerate
809
810 assign Y = |S ? Y_B : A;
811 endmodule
812