techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_INV_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$pos $bu0" *)
  43 module simplemap_buffers;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  48 module simplemap_bool_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  53 module simplemap_reduce_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  58 module simplemap_logic_ops;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$slice $concat $mux" *)
  63 module simplemap_various;
  64 endmodule
  65
  66 (* techmap_simplemap *)
  67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  68 module simplemap_registers;
  69 endmodule
  70
  71
  72 // --------------------------------------------------------
  73 // Trivial substitutions
  74 // --------------------------------------------------------
  75
  76 module \$neg (A, Y);
  77         parameter A_SIGNED = 0;
  78         parameter A_WIDTH = 1;
  79         parameter Y_WIDTH = 1;
  80
  81         input [A_WIDTH-1:0] A;
  82         output [Y_WIDTH-1:0] Y;
  83
  84         \$sub #(
  85                 .A_SIGNED(A_SIGNED),
  86                 .B_SIGNED(A_SIGNED),
  87                 .A_WIDTH(1),
  88                 .B_WIDTH(A_WIDTH),
  89                 .Y_WIDTH(Y_WIDTH)
  90         ) _TECHMAP_REPLACE_ (
  91                 .A(1'b0),
  92                 .B(A),
  93                 .Y(Y)
  94         );
  95 endmodule
  96
  97 module \$ge (A, B, Y);
  98         parameter A_SIGNED = 0;
  99         parameter B_SIGNED = 0;
 100         parameter A_WIDTH = 1;
 101         parameter B_WIDTH = 1;
 102         parameter Y_WIDTH = 1;
 103
 104         input [A_WIDTH-1:0] A;
 105         input [B_WIDTH-1:0] B;
 106         output [Y_WIDTH-1:0] Y;
 107
 108         \$le #(
 109                 .A_SIGNED(B_SIGNED),
 110                 .B_SIGNED(A_SIGNED),
 111                 .A_WIDTH(B_WIDTH),
 112                 .B_WIDTH(A_WIDTH),
 113                 .Y_WIDTH(Y_WIDTH)
 114         ) _TECHMAP_REPLACE_ (
 115                 .A(B),
 116                 .B(A),
 117                 .Y(Y)
 118         );
 119 endmodule
 120
 121 module \$gt (A, B, Y);
 122         parameter A_SIGNED = 0;
 123         parameter B_SIGNED = 0;
 124         parameter A_WIDTH = 1;
 125         parameter B_WIDTH = 1;
 126         parameter Y_WIDTH = 1;
 127
 128         input [A_WIDTH-1:0] A;
 129         input [B_WIDTH-1:0] B;
 130         output [Y_WIDTH-1:0] Y;
 131
 132         \$lt #(
 133                 .A_SIGNED(B_SIGNED),
 134                 .B_SIGNED(A_SIGNED),
 135                 .A_WIDTH(B_WIDTH),
 136                 .B_WIDTH(A_WIDTH),
 137                 .Y_WIDTH(Y_WIDTH)
 138         ) _TECHMAP_REPLACE_ (
 139                 .A(B),
 140                 .B(A),
 141                 .Y(Y)
 142         );
 143 endmodule
 144
 145
 146 // --------------------------------------------------------
 147 // Shift operators
 148 // --------------------------------------------------------
 149
 150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 152         parameter A_SIGNED = 0;
 153         parameter B_SIGNED = 0;
 154         parameter A_WIDTH = 1;
 155         parameter B_WIDTH = 1;
 156         parameter Y_WIDTH = 1;
 157
 158         parameter _TECHMAP_CELLTYPE_ = "";
 159         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 160         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 161
 162         input [A_WIDTH-1:0] A;
 163         input [B_WIDTH-1:0] B;
 164         output [Y_WIDTH-1:0] Y;
 165
 166         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 167         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 168
 169         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 170         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 171
 172         integer i;
 173         reg [WIDTH-1:0] buffer;
 174         reg overflow;
 175
 176         always @* begin
 177                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 178                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 179
 180                 for (i = 0; i < BB_WIDTH; i = i+1)
 181                         if (B[i]) begin
 182                                 if (shift_left)
 183                                         buffer = {buffer, (2**i)'b0};
 184                                 else if (2**i < WIDTH)
 185                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 186                                 else
 187                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 188                         end
 189         end
 190
 191         assign Y = buffer;
 192 endmodule
 193
 194 (* techmap_celltype = "$shift $shiftx" *)
 195 module shift_shiftx (A, B, Y);
 196         parameter A_SIGNED = 0;
 197         parameter B_SIGNED = 0;
 198         parameter A_WIDTH = 1;
 199         parameter B_WIDTH = 1;
 200         parameter Y_WIDTH = 1;
 201
 202         input [A_WIDTH-1:0] A;
 203         input [B_WIDTH-1:0] B;
 204         output [Y_WIDTH-1:0] Y;
 205
 206         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 207         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 208
 209         parameter _TECHMAP_CELLTYPE_ = "";
 210         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 211
 212         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 213         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 214
 215         integer i;
 216         reg [WIDTH-1:0] buffer;
 217         reg overflow;
 218
 219         always @* begin
 220                 overflow = 0;
 221                 buffer = {WIDTH{extbit}};
 222                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 223
 224                 if (B_WIDTH > BB_WIDTH) begin
 225                         if (B_SIGNED) begin
 226                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 227                                         if (B[i] != B[BB_WIDTH-1])
 228                                                 overflow = 1;
 229                         end else
 230                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 231                         if (overflow)
 232                                 buffer = {WIDTH{extbit}};
 233                 end
 234
 235                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 236                         if (B[i]) begin
 237                                 if (B_SIGNED && i == BB_WIDTH-1)
 238                                         buffer = {buffer, {2**i{extbit}}};
 239                                 else if (2**i < WIDTH)
 240                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 241                                 else
 242                                         buffer = {WIDTH{extbit}};
 243                         end
 244         end
 245
 246         assign Y = buffer;
 247 endmodule
 248
 249
 250 // --------------------------------------------------------
 251 // ALU Infrastructure
 252 // --------------------------------------------------------
 253
 254 module \$__alu_ripple (A, B, CI, Y, CO, CS);
 255         parameter WIDTH = 1;
 256
 257         input [WIDTH-1:0] A, B;
 258         output [WIDTH-1:0] Y;
 259
 260         input CI;
 261         output CO, CS;
 262
 263         wire [WIDTH:0] carry;
 264         assign carry[0] = CI;
 265         assign CO = carry[WIDTH];
 266         assign CS = carry[WIDTH-1];
 267
 268         genvar i;
 269         generate
 270                 for (i = 0; i < WIDTH; i = i+1)
 271                 begin:V
 272                         // {x, y} = a + b + c
 273                         wire a, b, c, x, y;
 274                         wire t1, t2, t3;
 275
 276                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(t1) );
 277                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(t2) );
 278                         \$_AND_ gate3 ( .A(t2), .B(c),  .Y(t3) );
 279                         \$_XOR_ gate4 ( .A(t2), .B(c),  .Y(y)  );
 280                         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(x)  );
 281
 282                         assign a = A[i], b = B[i], c = carry[i];
 283                         assign carry[i+1] = x, Y[i] = y;
 284                 end
 285         endgenerate
 286 endmodule
 287
 288 module \$__lcu_simple (P, G, CI, CO, PG, GG);
 289         parameter WIDTH = 1;
 290
 291         input [WIDTH-1:0] P, G;
 292         input CI;
 293
 294         output reg [WIDTH:0] CO;
 295         output reg PG, GG;
 296
 297         wire [1023:0] _TECHMAP_DO_ = "proc;;";
 298
 299         integer i, j;
 300         reg [WIDTH-1:0] tmp;
 301
 302         always @* begin
 303                 PG = &P;
 304                 GG = 0;
 305                 for (i = 0; i < WIDTH; i = i+1) begin
 306                         tmp = ~0;
 307                         tmp[i] = G[i];
 308                         for (j = i+1; j < WIDTH; j = j+1)
 309                                 tmp[j] = P[j];
 310                         GG = GG || &tmp[WIDTH-1:i];
 311                 end
 312
 313                 CO[0] = CI;
 314                 for (i = 0; i < WIDTH; i = i+1)
 315                         CO[i+1] = G[i] | (P[i] & CO[i]);
 316         end
 317 endmodule
 318
 319 module \$__lcu (P, G, CI, CO, PG, GG);
 320         parameter WIDTH = 1;
 321
 322         function integer get_group_size;
 323                 begin
 324                         get_group_size = 4;
 325                         while (4 * get_group_size < WIDTH)
 326                                 get_group_size = 4 * get_group_size;
 327                 end
 328         endfunction
 329
 330         input [WIDTH-1:0] P, G;
 331         input CI;
 332
 333         output [WIDTH:0] CO;
 334         output PG, GG;
 335
 336         genvar i;
 337         generate
 338                 if (WIDTH <= 4) begin
 339                         \$__lcu_simple #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO), .PG(PG), .GG(GG));
 340                 end else begin
 341                         localparam GROUP_SIZE = get_group_size();
 342                         localparam GROUPS_NUM = (WIDTH + GROUP_SIZE - 1) / GROUP_SIZE;
 343
 344                         wire [GROUPS_NUM-1:0] groups_p, groups_g;
 345                         wire [GROUPS_NUM:0] groups_ci;
 346
 347                         for (i = 0; i < GROUPS_NUM; i = i+1) begin:V
 348                                 localparam g_size = `MIN(GROUP_SIZE, WIDTH - i*GROUP_SIZE);
 349                                 localparam g_offset = i*GROUP_SIZE;
 350                                 wire [g_size:0] g_co;
 351
 352                                 \$__lcu #(.WIDTH(g_size)) g (.P(P[g_offset +: g_size]), .G(G[g_offset +: g_size]),
 353                                                 .CI(groups_ci[i]), .CO(g_co), .PG(groups_p[i]), .GG(groups_g[i]));
 354                                 assign CO[g_offset+1 +: g_size] = g_co[1 +: g_size];
 355                         end
 356
 357                         \$__lcu_simple #(.WIDTH(GROUPS_NUM)) super_lcu (.P(groups_p), .G(groups_g), .CI(CI), .CO(groups_ci), .PG(PG), .GG(GG));
 358
 359                         assign CO[0] = CI;
 360                 end
 361         endgenerate
 362 endmodule
 363
 364 module \$__alu_lookahead (A, B, CI, Y, CO, CS);
 365         parameter WIDTH = 1;
 366
 367         input [WIDTH-1:0] A, B;
 368         output [WIDTH-1:0] Y;
 369
 370         input CI;
 371         output CO, CS;
 372
 373         wire [WIDTH-1:0] P, G;
 374         wire [WIDTH:0] C;
 375
 376         assign CO = C[WIDTH];
 377         assign CS = C[WIDTH-1];
 378
 379         genvar i;
 380         generate
 381                 for (i = 0; i < WIDTH; i = i+1)
 382                 begin:V
 383                         wire a, b, c, p, g, y;
 384
 385                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(g) );
 386                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(p) );
 387                         \$_XOR_ gate3 ( .A(p),  .B(c),  .Y(y) );
 388
 389                         assign a = A[i], b = B[i], c = C[i];
 390                         assign P[i] = p, G[i] = g, Y[i] = y;
 391                 end
 392         endgenerate
 393
 394         \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
 395 endmodule
 396
 397 module \$__alu (A, B, CI, S, Y, CO, CS);
 398         parameter A_SIGNED = 0;
 399         parameter B_SIGNED = 0;
 400         parameter A_WIDTH = 1;
 401         parameter B_WIDTH = 1;
 402         parameter Y_WIDTH = 1;
 403
 404         input [A_WIDTH-1:0] A;
 405         input [B_WIDTH-1:0] B;
 406         output [Y_WIDTH-1:0] Y;
 407
 408         // carry in, sub, carry out, carry sign
 409         input CI, S;
 410         output CO, CS;
 411
 412         wire [Y_WIDTH-1:0] A_buf, B_buf;
 413         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 414         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 415
 416 `ifdef ALU_RIPPLE
 417         \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
 418 `else
 419         if (Y_WIDTH <= 4) begin
 420                 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
 421         end else begin
 422                 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
 423         end
 424 `endif
 425 endmodule
 426
 427
 428 // --------------------------------------------------------
 429 // ALU Cell Types: Compare, Add, Subtract
 430 // --------------------------------------------------------
 431
 432 `define ALU_COMMONS(_width, _ci, _s) """
 433         parameter A_SIGNED = 0;
 434         parameter B_SIGNED = 0;
 435         parameter A_WIDTH = 1;
 436         parameter B_WIDTH = 1;
 437         parameter Y_WIDTH = 1;
 438
 439         localparam WIDTH = _width;
 440
 441         input [A_WIDTH-1:0] A;
 442         input [B_WIDTH-1:0] B;
 443         output [Y_WIDTH-1:0] Y;
 444
 445         wire alu_co, alu_cs;
 446         wire [WIDTH-1:0] alu_y;
 447
 448         \$__alu #(
 449                 .A_SIGNED(A_SIGNED),
 450                 .B_SIGNED(B_SIGNED),
 451                 .A_WIDTH(A_WIDTH),
 452                 .B_WIDTH(B_WIDTH),
 453                 .Y_WIDTH(WIDTH)
 454         ) alu (
 455                 .A(A),
 456                 .B(B),
 457                 .CI(_ci),
 458                 .S(_s),
 459                 .Y(alu_y),
 460                 .CO(alu_co),
 461                 .CS(alu_cs)
 462         );
 463
 464         wire cf, of, zf, sf;
 465         assign cf = !alu_co;
 466         assign of = alu_co ^ alu_cs;
 467         assign zf = ~|alu_y;
 468         assign sf = alu_y[WIDTH-1];
 469 """
 470
 471 module \$lt (A, B, Y);
 472         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 473         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 474         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 475 endmodule
 476
 477 module \$le (A, B, Y);
 478         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 479         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 480         assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
 481 endmodule
 482
 483 module \$add (A, B, Y);
 484         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 485         `ALU_COMMONS(Y_WIDTH, 0, 0)
 486         assign Y = alu_y;
 487 endmodule
 488
 489 module \$sub (A, B, Y);
 490         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 491         `ALU_COMMONS(Y_WIDTH, 1, 1)
 492         assign Y = alu_y;
 493 endmodule
 494
 495
 496 // --------------------------------------------------------
 497 // Multiply
 498 // --------------------------------------------------------
 499
 500 module \$__arraymul (A, B, Y);
 501         parameter WIDTH = 8;
 502         input [WIDTH-1:0] A, B;
 503         output [WIDTH-1:0] Y;
 504
 505         wire [1023:0] _TECHMAP_DO_ = "proc;;";
 506
 507         integer i;
 508         reg [WIDTH-1:0] x, y;
 509
 510         always @* begin
 511                 x = B;
 512                 y = A[0] ? x : 0;
 513                 for (i = 1; i < WIDTH; i = i+1) begin
 514                         x = {x[WIDTH-2:0], 1'b0};
 515                         y = y + (A[i] ? x : 0);
 516                 end
 517         end
 518
 519         assign Y = y;
 520 endmodule
 521
 522 module \$mul (A, B, Y);
 523         parameter A_SIGNED = 0;
 524         parameter B_SIGNED = 0;
 525         parameter A_WIDTH = 1;
 526         parameter B_WIDTH = 1;
 527         parameter Y_WIDTH = 1;
 528
 529         input [A_WIDTH-1:0] A;
 530         input [B_WIDTH-1:0] B;
 531         output [Y_WIDTH-1:0] Y;
 532
 533         wire [Y_WIDTH-1:0] A_buf, B_buf;
 534         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 535         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 536
 537         \$__arraymul #(
 538                 .WIDTH(Y_WIDTH)
 539         ) arraymul (
 540                 .A(A_buf),
 541                 .B(B_buf),
 542                 .Y(Y)
 543         );
 544 endmodule
 545
 546
 547 // --------------------------------------------------------
 548 // Divide and Modulo
 549 // --------------------------------------------------------
 550
 551 module \$__div_mod_u (A, B, Y, R);
 552         parameter WIDTH = 1;
 553
 554         input [WIDTH-1:0] A, B;
 555         output [WIDTH-1:0] Y, R;
 556
 557         wire [WIDTH*WIDTH-1:0] chaindata;
 558         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 559
 560         genvar i;
 561         generate begin
 562                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 563                         wire [WIDTH-1:0] stage_in;
 564
 565                         if (i == 0) begin:cp
 566                                 assign stage_in = A;
 567                         end else begin:cp
 568                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 569                         end
 570
 571                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 572                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 573                 end
 574         end endgenerate
 575 endmodule
 576
 577 module \$__div_mod (A, B, Y, R);
 578         parameter A_SIGNED = 0;
 579         parameter B_SIGNED = 0;
 580         parameter A_WIDTH = 1;
 581         parameter B_WIDTH = 1;
 582         parameter Y_WIDTH = 1;
 583
 584         localparam WIDTH =
 585                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 586                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 587
 588         input [A_WIDTH-1:0] A;
 589         input [B_WIDTH-1:0] B;
 590         output [Y_WIDTH-1:0] Y, R;
 591
 592         wire [WIDTH-1:0] A_buf, B_buf;
 593         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 594         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 595
 596         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 597         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 598         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 599
 600         \$__div_mod_u #(
 601                 .WIDTH(WIDTH)
 602         ) div_mod_u (
 603                 .A(A_buf_u),
 604                 .B(B_buf_u),
 605                 .Y(Y_u),
 606                 .R(R_u)
 607         );
 608
 609         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 610         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 611 endmodule
 612
 613 module \$div (A, B, Y);
 614         parameter A_SIGNED = 0;
 615         parameter B_SIGNED = 0;
 616         parameter A_WIDTH = 1;
 617         parameter B_WIDTH = 1;
 618         parameter Y_WIDTH = 1;
 619
 620         input [A_WIDTH-1:0] A;
 621         input [B_WIDTH-1:0] B;
 622         output [Y_WIDTH-1:0] Y;
 623
 624         \$__div_mod #(
 625                 .A_SIGNED(A_SIGNED),
 626                 .B_SIGNED(B_SIGNED),
 627                 .A_WIDTH(A_WIDTH),
 628                 .B_WIDTH(B_WIDTH),
 629                 .Y_WIDTH(Y_WIDTH)
 630         ) div_mod (
 631                 .A(A),
 632                 .B(B),
 633                 .Y(Y)
 634         );
 635 endmodule
 636
 637 module \$mod (A, B, Y);
 638         parameter A_SIGNED = 0;
 639         parameter B_SIGNED = 0;
 640         parameter A_WIDTH = 1;
 641         parameter B_WIDTH = 1;
 642         parameter Y_WIDTH = 1;
 643
 644         input [A_WIDTH-1:0] A;
 645         input [B_WIDTH-1:0] B;
 646         output [Y_WIDTH-1:0] Y;
 647
 648         \$__div_mod #(
 649                 .A_SIGNED(A_SIGNED),
 650                 .B_SIGNED(B_SIGNED),
 651                 .A_WIDTH(A_WIDTH),
 652                 .B_WIDTH(B_WIDTH),
 653                 .Y_WIDTH(Y_WIDTH)
 654         ) div_mod (
 655                 .A(A),
 656                 .B(B),
 657                 .R(Y)
 658         );
 659 endmodule
 660
 661
 662 // --------------------------------------------------------
 663 // Power
 664 // --------------------------------------------------------
 665
 666 module \$pow (A, B, Y);
 667         parameter A_SIGNED = 0;
 668         parameter B_SIGNED = 0;
 669         parameter A_WIDTH = 1;
 670         parameter B_WIDTH = 1;
 671         parameter Y_WIDTH = 1;
 672
 673         input [A_WIDTH-1:0] A;
 674         input [B_WIDTH-1:0] B;
 675         output [Y_WIDTH-1:0] Y;
 676
 677         wire _TECHMAP_FAIL_ = 1;
 678 endmodule
 679
 680
 681 // --------------------------------------------------------
 682 // Equal and Not-Equal
 683 // --------------------------------------------------------
 684
 685 module \$eq (A, B, Y);
 686         parameter A_SIGNED = 0;
 687         parameter B_SIGNED = 0;
 688         parameter A_WIDTH = 1;
 689         parameter B_WIDTH = 1;
 690         parameter Y_WIDTH = 1;
 691
 692         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 693
 694         input [A_WIDTH-1:0] A;
 695         input [B_WIDTH-1:0] B;
 696         output [Y_WIDTH-1:0] Y;
 697
 698         wire carry, carry_sign;
 699         wire [WIDTH-1:0] A_buf, B_buf;
 700         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 701         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 702
 703         assign Y = ~|(A_buf ^ B_buf);
 704 endmodule
 705
 706 module \$ne (A, B, Y);
 707         parameter A_SIGNED = 0;
 708         parameter B_SIGNED = 0;
 709         parameter A_WIDTH = 1;
 710         parameter B_WIDTH = 1;
 711         parameter Y_WIDTH = 1;
 712
 713         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 714
 715         input [A_WIDTH-1:0] A;
 716         input [B_WIDTH-1:0] B;
 717         output [Y_WIDTH-1:0] Y;
 718
 719         wire carry, carry_sign;
 720         wire [WIDTH-1:0] A_buf, B_buf;
 721         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 722         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 723
 724         assign Y = |(A_buf ^ B_buf);
 725 endmodule
 726
 727 module \$eqx (A, B, Y);
 728         parameter A_SIGNED = 0;
 729         parameter B_SIGNED = 0;
 730         parameter A_WIDTH = 1;
 731         parameter B_WIDTH = 1;
 732         parameter Y_WIDTH = 1;
 733
 734         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 735
 736         input [A_WIDTH-1:0] A;
 737         input [B_WIDTH-1:0] B;
 738         output [Y_WIDTH-1:0] Y;
 739
 740         wire carry, carry_sign;
 741         wire [WIDTH-1:0] A_buf, B_buf;
 742         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 743         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 744
 745         assign Y = ~|(A_buf ^ B_buf);
 746 endmodule
 747
 748 module \$nex (A, B, Y);
 749         parameter A_SIGNED = 0;
 750         parameter B_SIGNED = 0;
 751         parameter A_WIDTH = 1;
 752         parameter B_WIDTH = 1;
 753         parameter Y_WIDTH = 1;
 754
 755         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 756
 757         input [A_WIDTH-1:0] A;
 758         input [B_WIDTH-1:0] B;
 759         output [Y_WIDTH-1:0] Y;
 760
 761         wire carry, carry_sign;
 762         wire [WIDTH-1:0] A_buf, B_buf;
 763         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 764         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 765
 766         assign Y = |(A_buf ^ B_buf);
 767 endmodule
 768
 769
 770 // --------------------------------------------------------
 771 // Parallel Multiplexers
 772 // --------------------------------------------------------
 773
 774 module \$pmux (A, B, S, Y);
 775         parameter WIDTH = 1;
 776         parameter S_WIDTH = 1;
 777
 778         input [WIDTH-1:0] A;
 779         input [WIDTH*S_WIDTH-1:0] B;
 780         input [S_WIDTH-1:0] S;
 781         output [WIDTH-1:0] Y;
 782
 783         wire [WIDTH-1:0] Y_B;
 784
 785         genvar i, j;
 786         generate
 787                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 788                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 789                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 790                 end:B_AND
 791                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 792                         wire [S_WIDTH-1:0] B_AND_BITS;
 793                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 794                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 795                         end:B_AND_BITS_COLLECT
 796                         assign Y_B[i] = |B_AND_BITS;
 797                 end:B_OR
 798         endgenerate
 799
 800         assign Y = |S ? Y_B : A;
 801 endmodule
 802