techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  43 module simplemap_bool_ops;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  48 module simplemap_reduce_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  53 module simplemap_logic_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$pos $slice $concat $mux" *)
  58 module simplemap_various;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  63 module simplemap_registers;
  64 endmodule
  65
  66
  67 // --------------------------------------------------------
  68 // Trivial substitutions
  69 // --------------------------------------------------------
  70
  71 module \$neg (A, Y);
  72         parameter A_SIGNED = 0;
  73         parameter A_WIDTH = 1;
  74         parameter Y_WIDTH = 1;
  75
  76         input [A_WIDTH-1:0] A;
  77         output [Y_WIDTH-1:0] Y;
  78
  79         \$sub #(
  80                 .A_SIGNED(A_SIGNED),
  81                 .B_SIGNED(A_SIGNED),
  82                 .A_WIDTH(1),
  83                 .B_WIDTH(A_WIDTH),
  84                 .Y_WIDTH(Y_WIDTH)
  85         ) _TECHMAP_REPLACE_ (
  86                 .A(1'b0),
  87                 .B(A),
  88                 .Y(Y)
  89         );
  90 endmodule
  91
  92 module \$ge (A, B, Y);
  93         parameter A_SIGNED = 0;
  94         parameter B_SIGNED = 0;
  95         parameter A_WIDTH = 1;
  96         parameter B_WIDTH = 1;
  97         parameter Y_WIDTH = 1;
  98
  99         input [A_WIDTH-1:0] A;
 100         input [B_WIDTH-1:0] B;
 101         output [Y_WIDTH-1:0] Y;
 102
 103         \$le #(
 104                 .A_SIGNED(B_SIGNED),
 105                 .B_SIGNED(A_SIGNED),
 106                 .A_WIDTH(B_WIDTH),
 107                 .B_WIDTH(A_WIDTH),
 108                 .Y_WIDTH(Y_WIDTH)
 109         ) _TECHMAP_REPLACE_ (
 110                 .A(B),
 111                 .B(A),
 112                 .Y(Y)
 113         );
 114 endmodule
 115
 116 module \$gt (A, B, Y);
 117         parameter A_SIGNED = 0;
 118         parameter B_SIGNED = 0;
 119         parameter A_WIDTH = 1;
 120         parameter B_WIDTH = 1;
 121         parameter Y_WIDTH = 1;
 122
 123         input [A_WIDTH-1:0] A;
 124         input [B_WIDTH-1:0] B;
 125         output [Y_WIDTH-1:0] Y;
 126
 127         \$lt #(
 128                 .A_SIGNED(B_SIGNED),
 129                 .B_SIGNED(A_SIGNED),
 130                 .A_WIDTH(B_WIDTH),
 131                 .B_WIDTH(A_WIDTH),
 132                 .Y_WIDTH(Y_WIDTH)
 133         ) _TECHMAP_REPLACE_ (
 134                 .A(B),
 135                 .B(A),
 136                 .Y(Y)
 137         );
 138 endmodule
 139
 140
 141 // --------------------------------------------------------
 142 // Shift operators
 143 // --------------------------------------------------------
 144
 145 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 146 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 147         parameter A_SIGNED = 0;
 148         parameter B_SIGNED = 0;
 149         parameter A_WIDTH = 1;
 150         parameter B_WIDTH = 1;
 151         parameter Y_WIDTH = 1;
 152
 153         parameter _TECHMAP_CELLTYPE_ = "";
 154         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 155         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 156
 157         input [A_WIDTH-1:0] A;
 158         input [B_WIDTH-1:0] B;
 159         output [Y_WIDTH-1:0] Y;
 160
 161         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 162         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 163
 164         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 165         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 166
 167         integer i;
 168         reg [WIDTH-1:0] buffer;
 169         reg overflow;
 170
 171         always @* begin
 172                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 173                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 174
 175                 for (i = 0; i < BB_WIDTH; i = i+1)
 176                         if (B[i]) begin
 177                                 if (shift_left)
 178                                         buffer = {buffer, (2**i)'b0};
 179                                 else if (2**i < WIDTH)
 180                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 181                                 else
 182                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 183                         end
 184         end
 185
 186         assign Y = buffer;
 187 endmodule
 188
 189 (* techmap_celltype = "$shift $shiftx" *)
 190 module shift_shiftx (A, B, Y);
 191         parameter A_SIGNED = 0;
 192         parameter B_SIGNED = 0;
 193         parameter A_WIDTH = 1;
 194         parameter B_WIDTH = 1;
 195         parameter Y_WIDTH = 1;
 196
 197         input [A_WIDTH-1:0] A;
 198         input [B_WIDTH-1:0] B;
 199         output [Y_WIDTH-1:0] Y;
 200
 201         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 202         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 203
 204         parameter _TECHMAP_CELLTYPE_ = "";
 205         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 206
 207         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 208         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 209
 210         integer i;
 211         reg [WIDTH-1:0] buffer;
 212         reg overflow;
 213
 214         always @* begin
 215                 overflow = 0;
 216                 buffer = {WIDTH{extbit}};
 217                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 218
 219                 if (B_WIDTH > BB_WIDTH) begin
 220                         if (B_SIGNED) begin
 221                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 222                                         if (B[i] != B[BB_WIDTH-1])
 223                                                 overflow = 1;
 224                         end else
 225                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 226                         if (overflow)
 227                                 buffer = {WIDTH{extbit}};
 228                 end
 229
 230                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 231                         if (B[i]) begin
 232                                 if (B_SIGNED && i == BB_WIDTH-1)
 233                                         buffer = {buffer, {2**i{extbit}}};
 234                                 else if (2**i < WIDTH)
 235                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 236                                 else
 237                                         buffer = {WIDTH{extbit}};
 238                         end
 239         end
 240
 241         assign Y = buffer;
 242 endmodule
 243
 244
 245 // --------------------------------------------------------
 246 // ALU Infrastructure
 247 // --------------------------------------------------------
 248
 249 module \$__alu_ripple (A, B, CI, X, Y, CO);
 250         parameter WIDTH = 1;
 251
 252         input [WIDTH-1:0] A, B;
 253         output [WIDTH-1:0] X, Y;
 254
 255         input CI;
 256         output [WIDTH-1:0] CO;
 257
 258         wire [WIDTH:0] carry;
 259         assign carry[0] = CI;
 260         assign CO = carry[WIDTH:1];
 261
 262         genvar i;
 263         generate
 264                 for (i = 0; i < WIDTH; i = i+1)
 265                 begin:V
 266                         // {x, y} = a + b + c
 267                         wire a, b, c, x, y;
 268                         wire t1, t2, t3;
 269
 270                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(t1) );
 271                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(t2) );
 272                         \$_AND_ gate3 ( .A(t2), .B(c),  .Y(t3) );
 273                         \$_XOR_ gate4 ( .A(t2), .B(c),  .Y(y)  );
 274                         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(x)  );
 275
 276                         assign a = A[i], b = B[i], c = carry[i];
 277                         assign carry[i+1] = x, X[i] = t2, Y[i] = y;
 278                 end
 279         endgenerate
 280 endmodule
 281
 282 module \$__lcu (P, G, CI, CO);
 283         parameter WIDTH = 2;
 284
 285         input [WIDTH-1:0] P, G;
 286         input CI;
 287
 288         output [WIDTH-1:0] CO;
 289
 290         integer i, j;
 291         reg [WIDTH-1:0] p, g;
 292
 293         wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
 294
 295         always @* begin
 296                 p = P;
 297                 g = G;
 298
 299                 // in almost all cases CI will be constant zero
 300                 g[0] = g[0] | (p[0] & CI);
 301
 302                 // [[CITE]] Brent Kung Adder
 303                 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
 304                 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
 305
 306                 // Main tree
 307                 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
 308                         for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
 309                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 310                                 p[j] = p[j] & p[j - 2**(i-1)];
 311                         end
 312                 end
 313
 314                 // Inverse tree
 315                 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
 316                         for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
 317                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 318                                 p[j] = p[j] & p[j - 2**(i-1)];
 319                         end
 320                 end
 321         end
 322
 323         assign CO = g;
 324 endmodule
 325
 326 module \$__alu_lookahead (A, B, CI, X, Y, CO);
 327         parameter WIDTH = 1;
 328
 329         input [WIDTH-1:0] A, B;
 330         output [WIDTH-1:0] X, Y;
 331
 332         input CI;
 333         output [WIDTH-1:0] CO;
 334
 335         wire [WIDTH-1:0] P, G;
 336         wire [WIDTH:0] carry;
 337
 338         genvar i;
 339         generate
 340                 for (i = 0; i < WIDTH; i = i+1)
 341                 begin:V
 342                         wire a, b, c, p, g, y;
 343
 344                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(g) );
 345                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(p) );
 346                         \$_XOR_ gate3 ( .A(p),  .B(c),  .Y(y) );
 347
 348                         assign a = A[i], b = B[i], c = carry[i];
 349                         assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
 350                 end
 351         endgenerate
 352
 353         \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
 354         assign carry = {CO, CI};
 355 endmodule
 356
 357 module \$alu (A, B, CI, BI, X, Y, CO);
 358         parameter A_SIGNED = 0;
 359         parameter B_SIGNED = 0;
 360         parameter A_WIDTH = 1;
 361         parameter B_WIDTH = 1;
 362         parameter Y_WIDTH = 1;
 363
 364         input [A_WIDTH-1:0] A;
 365         input [B_WIDTH-1:0] B;
 366         output [Y_WIDTH-1:0] X, Y;
 367
 368         input CI, BI;
 369         output [Y_WIDTH-1:0] CO;
 370
 371         wire [Y_WIDTH-1:0] A_buf, B_buf;
 372         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 373         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 374
 375 `ifdef ALU_RIPPLE
 376         \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 377 `else
 378         if (Y_WIDTH <= 4) begin
 379                 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 380         end else begin
 381                 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 382         end
 383 `endif
 384 endmodule
 385
 386
 387 // --------------------------------------------------------
 388 // ALU Cell Types: Compare, Add, Subtract
 389 // --------------------------------------------------------
 390
 391 `define ALU_COMMONS(_width, _sub) """
 392         parameter A_SIGNED = 0;
 393         parameter B_SIGNED = 0;
 394         parameter A_WIDTH = 1;
 395         parameter B_WIDTH = 1;
 396         parameter Y_WIDTH = 1;
 397
 398         localparam WIDTH = _width;
 399
 400         input [A_WIDTH-1:0] A;
 401         input [B_WIDTH-1:0] B;
 402         output [Y_WIDTH-1:0] Y;
 403
 404         wire [WIDTH-1:0] alu_x, alu_y, alu_co;
 405         wire [WIDTH:0] carry = {alu_co, |_sub};
 406
 407         \$alu #(
 408                 .A_SIGNED(A_SIGNED),
 409                 .B_SIGNED(B_SIGNED),
 410                 .A_WIDTH(A_WIDTH),
 411                 .B_WIDTH(B_WIDTH),
 412                 .Y_WIDTH(WIDTH)
 413         ) alu (
 414                 .A(A),
 415                 .B(B),
 416                 .CI(|_sub),
 417                 .BI(|_sub),
 418                 .X(alu_x),
 419                 .Y(alu_y),
 420                 .CO(alu_co)
 421         );
 422
 423         wire cf, of, zf, sf;
 424         assign cf = !carry[WIDTH];
 425         assign of = carry[WIDTH] ^ carry[WIDTH-1];
 426         assign sf = alu_y[WIDTH-1];
 427 """
 428
 429 module \$lt (A, B, Y);
 430         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 431         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 432         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 433 endmodule
 434
 435 module \$le (A, B, Y);
 436         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 437         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 438         assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
 439 endmodule
 440
 441 module \$add (A, B, Y);
 442         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 443         `ALU_COMMONS(Y_WIDTH, 0)
 444         assign Y = alu_y;
 445 endmodule
 446
 447 module \$sub (A, B, Y);
 448         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 449         `ALU_COMMONS(Y_WIDTH, 1)
 450         assign Y = alu_y;
 451 endmodule
 452
 453
 454 // --------------------------------------------------------
 455 // Multiply
 456 // --------------------------------------------------------
 457
 458 module \$__acc_set (acc_new, value);
 459         parameter WIDTH = 1;
 460         output reg [2*WIDTH-1:0] acc_new;
 461         input [WIDTH-1:0] value;
 462
 463         wire [1023:0] _TECHMAP_DO_ = "proc;;;";
 464
 465         integer k;
 466         always @* begin
 467                 for (k = 0; k < WIDTH; k = k+1) begin
 468                         acc_new[2*k +: 2] = value[k];
 469                 end
 470         end
 471 endmodule
 472
 473 module \$__acc_add (acc_new, acc_old, value);
 474         parameter WIDTH = 1;
 475         output reg [2*WIDTH-1:0] acc_new;
 476         input [2*WIDTH-1:0] acc_old;
 477         input [WIDTH-1:0] value;
 478
 479         wire [1023:0] _TECHMAP_DO_ = "proc; simplemap; opt -purge";
 480
 481         integer k;
 482         reg a, b, c;
 483
 484         always @* begin
 485                 for (k = 0; k < WIDTH; k = k+1) begin
 486                         a = acc_old[2*k];
 487                         b = k ? acc_old[2*k-1] : 1'b0;
 488                         c = value[k];
 489                         acc_new[2*k] = (a ^ b) ^ c;
 490                         acc_new[2*k+1] = (a & b) | ((a ^ b) & c);
 491                 end
 492         end
 493 endmodule
 494
 495 module \$__acc_get (value, acc);
 496         parameter WIDTH = 1;
 497         output reg [WIDTH-1:0] value;
 498         input [2*WIDTH-1:0] acc;
 499
 500         wire [1023:0] _TECHMAP_DO_ = "proc;;;";
 501
 502         integer k;
 503
 504         always @* begin
 505                 // at the end of the multiplier chain the carry-save accumulator
 506                 // should also have propagated all carries. thus we just need to
 507                 // copy the even bits from the carry accumulator to the output.
 508                 for (k = 0; k < WIDTH; k = k+1) begin
 509                         value[k] = acc[2*k];
 510                 end
 511         end
 512 endmodule
 513
 514 module \$__acc_mul (A, B, Y);
 515         parameter WIDTH = 1;
 516         input [WIDTH-1:0] A, B;
 517         output [WIDTH-1:0] Y;
 518
 519         wire [1023:0] _TECHMAP_DO_ = "proc;;";
 520
 521         integer i;
 522         reg [WIDTH-1:0] x;
 523         reg [2*WIDTH-1:0] y;
 524
 525         (* via_celltype = "\\$__acc_set acc_new" *)
 526         (* via_celltype_defparam_WIDTH = WIDTH *)
 527         function [2*WIDTH-1:0] acc_set;
 528                 input [WIDTH-1:0] value;
 529         endfunction
 530
 531         (* via_celltype = "\\$__acc_add acc_new" *)
 532         (* via_celltype_defparam_WIDTH = WIDTH *)
 533         function [2*WIDTH-1:0] acc_add;
 534                 input [2*WIDTH-1:0] acc_old;
 535                 input [WIDTH-1:0] value;
 536         endfunction
 537
 538         (* via_celltype = "\\$__acc_get value" *)
 539         (* via_celltype_defparam_WIDTH = WIDTH *)
 540         function [WIDTH-1:0] acc_get;
 541                 input [2*WIDTH-1:0] acc;
 542         endfunction
 543
 544         always @* begin
 545                 x = B;
 546                 y = acc_set(A[0] ? x : 1'b0);
 547                 for (i = 1; i < WIDTH; i = i+1) begin
 548                         x = {x[WIDTH-2:0], 1'b0};
 549                         y = acc_add(y, A[i] ? x : 1'b0);
 550                 end
 551         end
 552
 553         assign Y = acc_get(y);
 554 endmodule
 555
 556 module \$mul (A, B, Y);
 557         parameter A_SIGNED = 0;
 558         parameter B_SIGNED = 0;
 559         parameter A_WIDTH = 1;
 560         parameter B_WIDTH = 1;
 561         parameter Y_WIDTH = 1;
 562
 563         input [A_WIDTH-1:0] A;
 564         input [B_WIDTH-1:0] B;
 565         output [Y_WIDTH-1:0] Y;
 566
 567         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
 568
 569         wire [Y_WIDTH-1:0] A_buf, B_buf;
 570         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 571         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 572
 573         \$__acc_mul #(
 574                 .WIDTH(Y_WIDTH)
 575         ) _TECHMAP_REPLACE_ (
 576                 .A(A_buf),
 577                 .B(B_buf),
 578                 .Y(Y)
 579         );
 580 endmodule
 581
 582
 583 // --------------------------------------------------------
 584 // Divide and Modulo
 585 // --------------------------------------------------------
 586
 587 module \$__div_mod_u (A, B, Y, R);
 588         parameter WIDTH = 1;
 589
 590         input [WIDTH-1:0] A, B;
 591         output [WIDTH-1:0] Y, R;
 592
 593         wire [WIDTH*WIDTH-1:0] chaindata;
 594         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 595
 596         genvar i;
 597         generate begin
 598                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 599                         wire [WIDTH-1:0] stage_in;
 600
 601                         if (i == 0) begin:cp
 602                                 assign stage_in = A;
 603                         end else begin:cp
 604                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 605                         end
 606
 607                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 608                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 609                 end
 610         end endgenerate
 611 endmodule
 612
 613 module \$__div_mod (A, B, Y, R);
 614         parameter A_SIGNED = 0;
 615         parameter B_SIGNED = 0;
 616         parameter A_WIDTH = 1;
 617         parameter B_WIDTH = 1;
 618         parameter Y_WIDTH = 1;
 619
 620         localparam WIDTH =
 621                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 622                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 623
 624         input [A_WIDTH-1:0] A;
 625         input [B_WIDTH-1:0] B;
 626         output [Y_WIDTH-1:0] Y, R;
 627
 628         wire [WIDTH-1:0] A_buf, B_buf;
 629         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 630         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 631
 632         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 633         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 634         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 635
 636         \$__div_mod_u #(
 637                 .WIDTH(WIDTH)
 638         ) div_mod_u (
 639                 .A(A_buf_u),
 640                 .B(B_buf_u),
 641                 .Y(Y_u),
 642                 .R(R_u)
 643         );
 644
 645         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 646         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 647 endmodule
 648
 649 module \$div (A, B, Y);
 650         parameter A_SIGNED = 0;
 651         parameter B_SIGNED = 0;
 652         parameter A_WIDTH = 1;
 653         parameter B_WIDTH = 1;
 654         parameter Y_WIDTH = 1;
 655
 656         input [A_WIDTH-1:0] A;
 657         input [B_WIDTH-1:0] B;
 658         output [Y_WIDTH-1:0] Y;
 659
 660         \$__div_mod #(
 661                 .A_SIGNED(A_SIGNED),
 662                 .B_SIGNED(B_SIGNED),
 663                 .A_WIDTH(A_WIDTH),
 664                 .B_WIDTH(B_WIDTH),
 665                 .Y_WIDTH(Y_WIDTH)
 666         ) div_mod (
 667                 .A(A),
 668                 .B(B),
 669                 .Y(Y)
 670         );
 671 endmodule
 672
 673 module \$mod (A, B, Y);
 674         parameter A_SIGNED = 0;
 675         parameter B_SIGNED = 0;
 676         parameter A_WIDTH = 1;
 677         parameter B_WIDTH = 1;
 678         parameter Y_WIDTH = 1;
 679
 680         input [A_WIDTH-1:0] A;
 681         input [B_WIDTH-1:0] B;
 682         output [Y_WIDTH-1:0] Y;
 683
 684         \$__div_mod #(
 685                 .A_SIGNED(A_SIGNED),
 686                 .B_SIGNED(B_SIGNED),
 687                 .A_WIDTH(A_WIDTH),
 688                 .B_WIDTH(B_WIDTH),
 689                 .Y_WIDTH(Y_WIDTH)
 690         ) div_mod (
 691                 .A(A),
 692                 .B(B),
 693                 .R(Y)
 694         );
 695 endmodule
 696
 697
 698 // --------------------------------------------------------
 699 // Power
 700 // --------------------------------------------------------
 701
 702 module \$pow (A, B, Y);
 703         parameter A_SIGNED = 0;
 704         parameter B_SIGNED = 0;
 705         parameter A_WIDTH = 1;
 706         parameter B_WIDTH = 1;
 707         parameter Y_WIDTH = 1;
 708
 709         input [A_WIDTH-1:0] A;
 710         input [B_WIDTH-1:0] B;
 711         output [Y_WIDTH-1:0] Y;
 712
 713         wire _TECHMAP_FAIL_ = 1;
 714 endmodule
 715
 716
 717 // --------------------------------------------------------
 718 // Equal and Not-Equal
 719 // --------------------------------------------------------
 720
 721 module \$eq (A, B, Y);
 722         parameter A_SIGNED = 0;
 723         parameter B_SIGNED = 0;
 724         parameter A_WIDTH = 1;
 725         parameter B_WIDTH = 1;
 726         parameter Y_WIDTH = 1;
 727
 728         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 729
 730         input [A_WIDTH-1:0] A;
 731         input [B_WIDTH-1:0] B;
 732         output [Y_WIDTH-1:0] Y;
 733
 734         wire carry, carry_sign;
 735         wire [WIDTH-1:0] A_buf, B_buf;
 736         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 737         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 738
 739         assign Y = ~|(A_buf ^ B_buf);
 740 endmodule
 741
 742 module \$ne (A, B, Y);
 743         parameter A_SIGNED = 0;
 744         parameter B_SIGNED = 0;
 745         parameter A_WIDTH = 1;
 746         parameter B_WIDTH = 1;
 747         parameter Y_WIDTH = 1;
 748
 749         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 750
 751         input [A_WIDTH-1:0] A;
 752         input [B_WIDTH-1:0] B;
 753         output [Y_WIDTH-1:0] Y;
 754
 755         wire carry, carry_sign;
 756         wire [WIDTH-1:0] A_buf, B_buf;
 757         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 758         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 759
 760         assign Y = |(A_buf ^ B_buf);
 761 endmodule
 762
 763 module \$eqx (A, B, Y);
 764         parameter A_SIGNED = 0;
 765         parameter B_SIGNED = 0;
 766         parameter A_WIDTH = 1;
 767         parameter B_WIDTH = 1;
 768         parameter Y_WIDTH = 1;
 769
 770         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 771
 772         input [A_WIDTH-1:0] A;
 773         input [B_WIDTH-1:0] B;
 774         output [Y_WIDTH-1:0] Y;
 775
 776         wire carry, carry_sign;
 777         wire [WIDTH-1:0] A_buf, B_buf;
 778         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 779         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 780
 781         assign Y = ~|(A_buf ^ B_buf);
 782 endmodule
 783
 784 module \$nex (A, B, Y);
 785         parameter A_SIGNED = 0;
 786         parameter B_SIGNED = 0;
 787         parameter A_WIDTH = 1;
 788         parameter B_WIDTH = 1;
 789         parameter Y_WIDTH = 1;
 790
 791         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 792
 793         input [A_WIDTH-1:0] A;
 794         input [B_WIDTH-1:0] B;
 795         output [Y_WIDTH-1:0] Y;
 796
 797         wire carry, carry_sign;
 798         wire [WIDTH-1:0] A_buf, B_buf;
 799         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 800         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 801
 802         assign Y = |(A_buf ^ B_buf);
 803 endmodule
 804
 805
 806 // --------------------------------------------------------
 807 // Parallel Multiplexers
 808 // --------------------------------------------------------
 809
 810 module \$pmux (A, B, S, Y);
 811         parameter WIDTH = 1;
 812         parameter S_WIDTH = 1;
 813
 814         input [WIDTH-1:0] A;
 815         input [WIDTH*S_WIDTH-1:0] B;
 816         input [S_WIDTH-1:0] S;
 817         output [WIDTH-1:0] Y;
 818
 819         wire [WIDTH-1:0] Y_B;
 820
 821         genvar i, j;
 822         generate
 823                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 824                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 825                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 826                 end:B_AND
 827                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 828                         wire [S_WIDTH-1:0] B_AND_BITS;
 829                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 830                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 831                         end:B_AND_BITS_COLLECT
 832                         assign Y_B[i] = |B_AND_BITS;
 833                 end:B_OR
 834         endgenerate
 835
 836         assign Y = |S ? Y_B : A;
 837 endmodule
 838
 839
 840 // --------------------------------------------------------
 841 // LUTs
 842 // --------------------------------------------------------
 843
 844 `ifndef NOLUT
 845 module \$lut (A, Y);
 846         parameter WIDTH = 1;
 847         parameter LUT = 0;
 848
 849         input [WIDTH-1:0] A;
 850         output Y;
 851
 852         assign Y = LUT[A];
 853 endmodule
 854 `endif
 855