techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  43 module simplemap_bool_ops;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  48 module simplemap_reduce_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  53 module simplemap_logic_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$pos $slice $concat $mux" *)
  58 module simplemap_various;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  63 module simplemap_registers;
  64 endmodule
  65
  66
  67 // --------------------------------------------------------
  68 // Trivial substitutions
  69 // --------------------------------------------------------
  70
  71 module \$neg (A, Y);
  72         parameter A_SIGNED = 0;
  73         parameter A_WIDTH = 1;
  74         parameter Y_WIDTH = 1;
  75
  76         input [A_WIDTH-1:0] A;
  77         output [Y_WIDTH-1:0] Y;
  78
  79         \$sub #(
  80                 .A_SIGNED(A_SIGNED),
  81                 .B_SIGNED(A_SIGNED),
  82                 .A_WIDTH(1),
  83                 .B_WIDTH(A_WIDTH),
  84                 .Y_WIDTH(Y_WIDTH)
  85         ) _TECHMAP_REPLACE_ (
  86                 .A(1'b0),
  87                 .B(A),
  88                 .Y(Y)
  89         );
  90 endmodule
  91
  92 module \$ge (A, B, Y);
  93         parameter A_SIGNED = 0;
  94         parameter B_SIGNED = 0;
  95         parameter A_WIDTH = 1;
  96         parameter B_WIDTH = 1;
  97         parameter Y_WIDTH = 1;
  98
  99         input [A_WIDTH-1:0] A;
 100         input [B_WIDTH-1:0] B;
 101         output [Y_WIDTH-1:0] Y;
 102
 103         \$le #(
 104                 .A_SIGNED(B_SIGNED),
 105                 .B_SIGNED(A_SIGNED),
 106                 .A_WIDTH(B_WIDTH),
 107                 .B_WIDTH(A_WIDTH),
 108                 .Y_WIDTH(Y_WIDTH)
 109         ) _TECHMAP_REPLACE_ (
 110                 .A(B),
 111                 .B(A),
 112                 .Y(Y)
 113         );
 114 endmodule
 115
 116 module \$gt (A, B, Y);
 117         parameter A_SIGNED = 0;
 118         parameter B_SIGNED = 0;
 119         parameter A_WIDTH = 1;
 120         parameter B_WIDTH = 1;
 121         parameter Y_WIDTH = 1;
 122
 123         input [A_WIDTH-1:0] A;
 124         input [B_WIDTH-1:0] B;
 125         output [Y_WIDTH-1:0] Y;
 126
 127         \$lt #(
 128                 .A_SIGNED(B_SIGNED),
 129                 .B_SIGNED(A_SIGNED),
 130                 .A_WIDTH(B_WIDTH),
 131                 .B_WIDTH(A_WIDTH),
 132                 .Y_WIDTH(Y_WIDTH)
 133         ) _TECHMAP_REPLACE_ (
 134                 .A(B),
 135                 .B(A),
 136                 .Y(Y)
 137         );
 138 endmodule
 139
 140
 141 // --------------------------------------------------------
 142 // Shift operators
 143 // --------------------------------------------------------
 144
 145 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 146 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 147         parameter A_SIGNED = 0;
 148         parameter B_SIGNED = 0;
 149         parameter A_WIDTH = 1;
 150         parameter B_WIDTH = 1;
 151         parameter Y_WIDTH = 1;
 152
 153         parameter _TECHMAP_CELLTYPE_ = "";
 154         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 155         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 156
 157         input [A_WIDTH-1:0] A;
 158         input [B_WIDTH-1:0] B;
 159         output [Y_WIDTH-1:0] Y;
 160
 161         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 162         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 163
 164         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 165         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 166
 167         integer i;
 168         reg [WIDTH-1:0] buffer;
 169         reg overflow;
 170
 171         always @* begin
 172                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 173                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 174
 175                 for (i = 0; i < BB_WIDTH; i = i+1)
 176                         if (B[i]) begin
 177                                 if (shift_left)
 178                                         buffer = {buffer, (2**i)'b0};
 179                                 else if (2**i < WIDTH)
 180                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 181                                 else
 182                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 183                         end
 184         end
 185
 186         assign Y = buffer;
 187 endmodule
 188
 189 (* techmap_celltype = "$shift $shiftx" *)
 190 module shift_shiftx (A, B, Y);
 191         parameter A_SIGNED = 0;
 192         parameter B_SIGNED = 0;
 193         parameter A_WIDTH = 1;
 194         parameter B_WIDTH = 1;
 195         parameter Y_WIDTH = 1;
 196
 197         input [A_WIDTH-1:0] A;
 198         input [B_WIDTH-1:0] B;
 199         output [Y_WIDTH-1:0] Y;
 200
 201         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 202         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 203
 204         parameter _TECHMAP_CELLTYPE_ = "";
 205         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 206
 207         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 208         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 209
 210         integer i;
 211         reg [WIDTH-1:0] buffer;
 212         reg overflow;
 213
 214         always @* begin
 215                 overflow = 0;
 216                 buffer = {WIDTH{extbit}};
 217                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 218
 219                 if (B_WIDTH > BB_WIDTH) begin
 220                         if (B_SIGNED) begin
 221                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 222                                         if (B[i] != B[BB_WIDTH-1])
 223                                                 overflow = 1;
 224                         end else
 225                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 226                         if (overflow)
 227                                 buffer = {WIDTH{extbit}};
 228                 end
 229
 230                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 231                         if (B[i]) begin
 232                                 if (B_SIGNED && i == BB_WIDTH-1)
 233                                         buffer = {buffer, {2**i{extbit}}};
 234                                 else if (2**i < WIDTH)
 235                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 236                                 else
 237                                         buffer = {WIDTH{extbit}};
 238                         end
 239         end
 240
 241         assign Y = buffer;
 242 endmodule
 243
 244
 245 // --------------------------------------------------------
 246 // ALU Infrastructure
 247 // --------------------------------------------------------
 248
 249 module \$__alu_ripple (A, B, CI, X, Y, CO);
 250         parameter WIDTH = 1;
 251
 252         input [WIDTH-1:0] A, B;
 253         output [WIDTH-1:0] X, Y;
 254
 255         input CI;
 256         output [WIDTH-1:0] CO;
 257
 258         wire [WIDTH:0] carry;
 259         assign carry[0] = CI;
 260         assign CO = carry[WIDTH:1];
 261
 262         genvar i;
 263         generate
 264                 for (i = 0; i < WIDTH; i = i+1)
 265                 begin:V
 266                         // {x, y} = a + b + c
 267                         wire a, b, c, x, y;
 268                         wire t1, t2, t3;
 269
 270                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(t1) );
 271                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(t2) );
 272                         \$_AND_ gate3 ( .A(t2), .B(c),  .Y(t3) );
 273                         \$_XOR_ gate4 ( .A(t2), .B(c),  .Y(y)  );
 274                         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(x)  );
 275
 276                         assign a = A[i], b = B[i], c = carry[i];
 277                         assign carry[i+1] = x, X[i] = t2, Y[i] = y;
 278                 end
 279         endgenerate
 280 endmodule
 281
 282 module \$__lcu (P, G, CI, CO);
 283         parameter WIDTH = 2;
 284
 285         input [WIDTH-1:0] P, G;
 286         input CI;
 287
 288         output [WIDTH-1:0] CO;
 289
 290         integer i, j;
 291         reg [WIDTH-1:0] p, g;
 292
 293         wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
 294
 295         always @* begin
 296                 p = P;
 297                 g = G;
 298
 299                 // in almost all cases CI will be constant zero
 300                 g[0] = g[0] | (p[0] & CI);
 301
 302                 // [[CITE]] Brent Kung Adder
 303                 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
 304                 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
 305
 306                 // Main tree
 307                 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
 308                         for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
 309                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 310                                 p[j] = p[j] & p[j - 2**(i-1)];
 311                         end
 312                 end
 313
 314                 // Inverse tree
 315                 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
 316                         for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
 317                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 318                                 p[j] = p[j] & p[j - 2**(i-1)];
 319                         end
 320                 end
 321         end
 322
 323         assign CO = g;
 324 endmodule
 325
 326 module \$__alu_lookahead (A, B, CI, X, Y, CO);
 327         parameter WIDTH = 1;
 328
 329         input [WIDTH-1:0] A, B;
 330         output [WIDTH-1:0] X, Y;
 331
 332         input CI;
 333         output [WIDTH-1:0] CO;
 334
 335         wire [WIDTH-1:0] P, G;
 336         wire [WIDTH:0] carry;
 337
 338         genvar i;
 339         generate
 340                 for (i = 0; i < WIDTH; i = i+1)
 341                 begin:V
 342                         wire a, b, c, p, g, y;
 343
 344                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(g) );
 345                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(p) );
 346                         \$_XOR_ gate3 ( .A(p),  .B(c),  .Y(y) );
 347
 348                         assign a = A[i], b = B[i], c = carry[i];
 349                         assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
 350                 end
 351         endgenerate
 352
 353         \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
 354         assign carry = {CO, CI};
 355 endmodule
 356
 357 module \$alu (A, B, CI, BI, X, Y, CO);
 358         parameter A_SIGNED = 0;
 359         parameter B_SIGNED = 0;
 360         parameter A_WIDTH = 1;
 361         parameter B_WIDTH = 1;
 362         parameter Y_WIDTH = 1;
 363
 364         input [A_WIDTH-1:0] A;
 365         input [B_WIDTH-1:0] B;
 366         output [Y_WIDTH-1:0] X, Y;
 367
 368         input CI, BI;
 369         output [Y_WIDTH-1:0] CO;
 370
 371         wire [Y_WIDTH-1:0] A_buf, B_buf;
 372         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 373         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 374
 375 `ifdef ALU_RIPPLE
 376         \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 377 `else
 378         if (Y_WIDTH <= 4) begin
 379                 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 380         end else begin
 381                 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 382         end
 383 `endif
 384 endmodule
 385
 386
 387 // --------------------------------------------------------
 388 // ALU Cell Types: Compare, Add, Subtract
 389 // --------------------------------------------------------
 390
 391 `define ALU_COMMONS(_width, _sub) """
 392         parameter A_SIGNED = 0;
 393         parameter B_SIGNED = 0;
 394         parameter A_WIDTH = 1;
 395         parameter B_WIDTH = 1;
 396         parameter Y_WIDTH = 1;
 397
 398         localparam WIDTH = _width;
 399
 400         input [A_WIDTH-1:0] A;
 401         input [B_WIDTH-1:0] B;
 402         output [Y_WIDTH-1:0] Y;
 403
 404         wire [WIDTH-1:0] alu_x, alu_y, alu_co;
 405         wire [WIDTH:0] carry = {alu_co, |_sub};
 406
 407         \$alu #(
 408                 .A_SIGNED(A_SIGNED),
 409                 .B_SIGNED(B_SIGNED),
 410                 .A_WIDTH(A_WIDTH),
 411                 .B_WIDTH(B_WIDTH),
 412                 .Y_WIDTH(WIDTH)
 413         ) alu (
 414                 .A(A),
 415                 .B(B),
 416                 .CI(|_sub),
 417                 .BI(|_sub),
 418                 .X(alu_x),
 419                 .Y(alu_y),
 420                 .CO(alu_co)
 421         );
 422
 423         wire cf, of, zf, sf;
 424         assign cf = !carry[WIDTH];
 425         assign of = carry[WIDTH] ^ carry[WIDTH-1];
 426         assign sf = alu_y[WIDTH-1];
 427 """
 428
 429 module \$lt (A, B, Y);
 430         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 431         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 432         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 433 endmodule
 434
 435 module \$le (A, B, Y);
 436         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 437         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 438         assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
 439 endmodule
 440
 441 module \$add (A, B, Y);
 442         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 443         `ALU_COMMONS(Y_WIDTH, 0)
 444         assign Y = alu_y;
 445 endmodule
 446
 447 module \$sub (A, B, Y);
 448         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 449         `ALU_COMMONS(Y_WIDTH, 1)
 450         assign Y = alu_y;
 451 endmodule
 452
 453
 454 // --------------------------------------------------------
 455 // Multiply
 456 // --------------------------------------------------------
 457
 458 module \$__acc_set (acc_new, value);
 459         parameter WIDTH = 1;
 460         output reg [2*WIDTH-1:0] acc_new;
 461         input [WIDTH-1:0] value;
 462
 463         wire [1023:0] _TECHMAP_DO_ = "proc;;;";
 464
 465         integer k;
 466         always @* begin
 467                 for (k = 0; k < WIDTH; k = k+1) begin
 468                         acc_new[2*k +: 2] = value[k];
 469                 end
 470         end
 471 endmodule
 472
 473 module \$__acc_add (acc_new, acc_old, value);
 474         parameter WIDTH = 1;
 475         output reg [2*WIDTH-1:0] acc_new;
 476         input [2*WIDTH-1:0] acc_old;
 477         input [WIDTH-1:0] value;
 478
 479         wire [1023:0] _TECHMAP_DO_ = "proc; simplemap; opt -purge";
 480
 481         integer k;
 482         reg a, b, c;
 483
 484         always @* begin
 485                 for (k = 0; k < WIDTH; k = k+1) begin
 486                         a = acc_old[2*k];
 487                         b = k ? acc_old[2*k-1] : 1'b0;
 488                         c = value[k];
 489                         acc_new[2*k] = (a ^ b) ^ c;
 490                         acc_new[2*k+1] = (a & b) | ((a ^ b) & c);
 491                 end
 492         end
 493 endmodule
 494
 495 module \$__acc_get (value, acc);
 496         parameter WIDTH = 1;
 497         output reg [WIDTH-1:0] value;
 498         input [2*WIDTH-1:0] acc;
 499
 500         wire [1023:0] _TECHMAP_DO_ = "proc;;;";
 501
 502         integer k;
 503
 504         always @* begin
 505                 // at the end of the multiplier chain the carry-save accumulator
 506                 // should also have propagated all carries. thus we just need to
 507                 // copy the even bits from the carry accumulator to the output.
 508                 for (k = 0; k < WIDTH; k = k+1) begin
 509                         value[k] = acc[2*k];
 510                 end
 511         end
 512 endmodule
 513
 514 module \$__acc_mul (A, B, Y);
 515         parameter WIDTH = 1;
 516         input [WIDTH-1:0] A, B;
 517         output [WIDTH-1:0] Y;
 518
 519         wire [1023:0] _TECHMAP_DO_ = "proc;;";
 520
 521         integer i;
 522         reg [WIDTH-1:0] x;
 523         reg [2*WIDTH-1:0] y;
 524
 525         (* via_celltype = "\\$__acc_set acc_new" *)
 526         (* via_celltype_defparam_WIDTH = WIDTH *)
 527         function [2*WIDTH-1:0] acc_set;
 528                 input [WIDTH-1:0] value;
 529         endfunction
 530
 531         (* via_celltype = "\\$__acc_add acc_new" *)
 532         (* via_celltype_defparam_WIDTH = WIDTH *)
 533         function [2*WIDTH-1:0] acc_add;
 534                 input [2*WIDTH-1:0] acc_old;
 535                 input [WIDTH-1:0] value;
 536         endfunction
 537
 538         (* via_celltype = "\\$__acc_get value" *)
 539         (* via_celltype_defparam_WIDTH = WIDTH *)
 540         function [WIDTH-1:0] acc_get;
 541                 input [2*WIDTH-1:0] acc;
 542         endfunction
 543
 544         always @* begin
 545                 x = B;
 546                 y = acc_set(A[0] ? x : 1'b0);
 547                 for (i = 1; i < WIDTH; i = i+1) begin
 548                         x = {x[WIDTH-2:0], 1'b0};
 549                         y = acc_add(y, A[i] ? x : 1'b0);
 550                 end
 551         end
 552
 553         assign Y = acc_get(y);
 554 endmodule
 555
 556 module \$mul (A, B, Y);
 557         parameter A_SIGNED = 0;
 558         parameter B_SIGNED = 0;
 559         parameter A_WIDTH = 1;
 560         parameter B_WIDTH = 1;
 561         parameter Y_WIDTH = 1;
 562
 563         input [A_WIDTH-1:0] A;
 564         input [B_WIDTH-1:0] B;
 565         output [Y_WIDTH-1:0] Y;
 566
 567         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
 568
 569         wire [Y_WIDTH-1:0] A_buf, B_buf;
 570         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 571         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 572
 573         \$__acc_mul #(
 574                 .WIDTH(Y_WIDTH)
 575         ) _TECHMAP_REPLACE_ (
 576                 .A(A_buf),
 577                 .B(B_buf),
 578                 .Y(Y)
 579         );
 580 endmodule
 581
 582 module \$macc (A, B, Y);
 583         parameter A_WIDTH = 0;
 584         parameter B_WIDTH = 0;
 585         parameter Y_WIDTH = 0;
 586         parameter CONFIG = 4'b0000;
 587         parameter CONFIG_WIDTH = 4;
 588
 589         input [A_WIDTH-1:0] A;
 590         input [B_WIDTH-1:0] B;
 591         output reg [Y_WIDTH-1:0] Y;
 592
 593         wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
 594
 595         localparam integer num_bits = CONFIG[3:0];
 596         localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
 597         localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
 598
 599         function [2*num_ports*num_abits-1:0] get_port_offsets;
 600                 input [CONFIG_WIDTH-1:0] cfg;
 601                 integer i, cursor;
 602                 begin
 603                         cursor = 0;
 604                         get_port_offsets = 0;
 605                         for (i = 0; i < num_ports; i = i+1) begin
 606                                 get_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;
 607                                 cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];
 608                                 get_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;
 609                                 cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];
 610                         end
 611                 end
 612         endfunction
 613
 614         localparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);
 615
 616         `define PORT_IS_SIGNED   (0 + CONFIG[4 + i*(2 + 2*num_bits)])
 617         `define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])
 618         `define PORT_SIZE_A      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])
 619         `define PORT_SIZE_B      (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])
 620         `define PORT_OFFSET_A    (0 + port_offsets[2*i*num_abits +: num_abits])
 621         `define PORT_OFFSET_B    (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])
 622
 623         integer i, j;
 624         reg [Y_WIDTH-1:0] tmp_a, tmp_b;
 625
 626         always @* begin
 627                 Y = 0;
 628                 for (i = 0; i < num_ports; i = i+1)
 629                 begin
 630                         tmp_a = 0;
 631                         tmp_b = 0;
 632
 633                         for (j = 0; j < `PORT_SIZE_A; j = j+1)
 634                                 tmp_a[j] = A[`PORT_OFFSET_A + j];
 635
 636                         if (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)
 637                                 for (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)
 638                                         tmp_a[j] = tmp_a[`PORT_SIZE_A-1];
 639
 640                         for (j = 0; j < `PORT_SIZE_B; j = j+1)
 641                                 tmp_b[j] = A[`PORT_OFFSET_B + j];
 642
 643                         if (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)
 644                                 for (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)
 645                                         tmp_b[j] = tmp_b[`PORT_SIZE_B-1];
 646
 647                         if (`PORT_SIZE_B > 0)
 648                                 tmp_a = tmp_a * tmp_b;
 649
 650                         if (`PORT_DO_SUBTRACT)
 651                                 Y = Y - tmp_a;
 652                         else
 653                                 Y = Y + tmp_a;
 654                 end
 655                 for (i = 0; i < B_WIDTH; i = i+1) begin
 656                         Y = Y + B[i];
 657                 end
 658         end
 659
 660         `undef PORT_IS_SIGNED
 661         `undef PORT_DO_SUBTRACT
 662         `undef PORT_SIZE_A
 663         `undef PORT_SIZE_B
 664         `undef PORT_OFFSET_A
 665         `undef PORT_OFFSET_B
 666 endmodule
 667
 668
 669 // --------------------------------------------------------
 670 // Divide and Modulo
 671 // --------------------------------------------------------
 672
 673 module \$__div_mod_u (A, B, Y, R);
 674         parameter WIDTH = 1;
 675
 676         input [WIDTH-1:0] A, B;
 677         output [WIDTH-1:0] Y, R;
 678
 679         wire [WIDTH*WIDTH-1:0] chaindata;
 680         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 681
 682         genvar i;
 683         generate begin
 684                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 685                         wire [WIDTH-1:0] stage_in;
 686
 687                         if (i == 0) begin:cp
 688                                 assign stage_in = A;
 689                         end else begin:cp
 690                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 691                         end
 692
 693                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 694                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 695                 end
 696         end endgenerate
 697 endmodule
 698
 699 module \$__div_mod (A, B, Y, R);
 700         parameter A_SIGNED = 0;
 701         parameter B_SIGNED = 0;
 702         parameter A_WIDTH = 1;
 703         parameter B_WIDTH = 1;
 704         parameter Y_WIDTH = 1;
 705
 706         localparam WIDTH =
 707                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 708                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 709
 710         input [A_WIDTH-1:0] A;
 711         input [B_WIDTH-1:0] B;
 712         output [Y_WIDTH-1:0] Y, R;
 713
 714         wire [WIDTH-1:0] A_buf, B_buf;
 715         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 716         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 717
 718         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 719         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 720         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 721
 722         \$__div_mod_u #(
 723                 .WIDTH(WIDTH)
 724         ) div_mod_u (
 725                 .A(A_buf_u),
 726                 .B(B_buf_u),
 727                 .Y(Y_u),
 728                 .R(R_u)
 729         );
 730
 731         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 732         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 733 endmodule
 734
 735 module \$div (A, B, Y);
 736         parameter A_SIGNED = 0;
 737         parameter B_SIGNED = 0;
 738         parameter A_WIDTH = 1;
 739         parameter B_WIDTH = 1;
 740         parameter Y_WIDTH = 1;
 741
 742         input [A_WIDTH-1:0] A;
 743         input [B_WIDTH-1:0] B;
 744         output [Y_WIDTH-1:0] Y;
 745
 746         \$__div_mod #(
 747                 .A_SIGNED(A_SIGNED),
 748                 .B_SIGNED(B_SIGNED),
 749                 .A_WIDTH(A_WIDTH),
 750                 .B_WIDTH(B_WIDTH),
 751                 .Y_WIDTH(Y_WIDTH)
 752         ) div_mod (
 753                 .A(A),
 754                 .B(B),
 755                 .Y(Y)
 756         );
 757 endmodule
 758
 759 module \$mod (A, B, Y);
 760         parameter A_SIGNED = 0;
 761         parameter B_SIGNED = 0;
 762         parameter A_WIDTH = 1;
 763         parameter B_WIDTH = 1;
 764         parameter Y_WIDTH = 1;
 765
 766         input [A_WIDTH-1:0] A;
 767         input [B_WIDTH-1:0] B;
 768         output [Y_WIDTH-1:0] Y;
 769
 770         \$__div_mod #(
 771                 .A_SIGNED(A_SIGNED),
 772                 .B_SIGNED(B_SIGNED),
 773                 .A_WIDTH(A_WIDTH),
 774                 .B_WIDTH(B_WIDTH),
 775                 .Y_WIDTH(Y_WIDTH)
 776         ) div_mod (
 777                 .A(A),
 778                 .B(B),
 779                 .R(Y)
 780         );
 781 endmodule
 782
 783
 784 // --------------------------------------------------------
 785 // Power
 786 // --------------------------------------------------------
 787
 788 module \$pow (A, B, Y);
 789         parameter A_SIGNED = 0;
 790         parameter B_SIGNED = 0;
 791         parameter A_WIDTH = 1;
 792         parameter B_WIDTH = 1;
 793         parameter Y_WIDTH = 1;
 794
 795         input [A_WIDTH-1:0] A;
 796         input [B_WIDTH-1:0] B;
 797         output [Y_WIDTH-1:0] Y;
 798
 799         wire _TECHMAP_FAIL_ = 1;
 800 endmodule
 801
 802
 803 // --------------------------------------------------------
 804 // Equal and Not-Equal
 805 // --------------------------------------------------------
 806
 807 module \$eq (A, B, Y);
 808         parameter A_SIGNED = 0;
 809         parameter B_SIGNED = 0;
 810         parameter A_WIDTH = 1;
 811         parameter B_WIDTH = 1;
 812         parameter Y_WIDTH = 1;
 813
 814         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 815
 816         input [A_WIDTH-1:0] A;
 817         input [B_WIDTH-1:0] B;
 818         output [Y_WIDTH-1:0] Y;
 819
 820         wire carry, carry_sign;
 821         wire [WIDTH-1:0] A_buf, B_buf;
 822         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 823         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 824
 825         assign Y = ~|(A_buf ^ B_buf);
 826 endmodule
 827
 828 module \$ne (A, B, Y);
 829         parameter A_SIGNED = 0;
 830         parameter B_SIGNED = 0;
 831         parameter A_WIDTH = 1;
 832         parameter B_WIDTH = 1;
 833         parameter Y_WIDTH = 1;
 834
 835         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 836
 837         input [A_WIDTH-1:0] A;
 838         input [B_WIDTH-1:0] B;
 839         output [Y_WIDTH-1:0] Y;
 840
 841         wire carry, carry_sign;
 842         wire [WIDTH-1:0] A_buf, B_buf;
 843         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 844         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 845
 846         assign Y = |(A_buf ^ B_buf);
 847 endmodule
 848
 849 module \$eqx (A, B, Y);
 850         parameter A_SIGNED = 0;
 851         parameter B_SIGNED = 0;
 852         parameter A_WIDTH = 1;
 853         parameter B_WIDTH = 1;
 854         parameter Y_WIDTH = 1;
 855
 856         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 857
 858         input [A_WIDTH-1:0] A;
 859         input [B_WIDTH-1:0] B;
 860         output [Y_WIDTH-1:0] Y;
 861
 862         wire carry, carry_sign;
 863         wire [WIDTH-1:0] A_buf, B_buf;
 864         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 865         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 866
 867         assign Y = ~|(A_buf ^ B_buf);
 868 endmodule
 869
 870 module \$nex (A, B, Y);
 871         parameter A_SIGNED = 0;
 872         parameter B_SIGNED = 0;
 873         parameter A_WIDTH = 1;
 874         parameter B_WIDTH = 1;
 875         parameter Y_WIDTH = 1;
 876
 877         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 878
 879         input [A_WIDTH-1:0] A;
 880         input [B_WIDTH-1:0] B;
 881         output [Y_WIDTH-1:0] Y;
 882
 883         wire carry, carry_sign;
 884         wire [WIDTH-1:0] A_buf, B_buf;
 885         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 886         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 887
 888         assign Y = |(A_buf ^ B_buf);
 889 endmodule
 890
 891
 892 // --------------------------------------------------------
 893 // Parallel Multiplexers
 894 // --------------------------------------------------------
 895
 896 module \$pmux (A, B, S, Y);
 897         parameter WIDTH = 1;
 898         parameter S_WIDTH = 1;
 899
 900         input [WIDTH-1:0] A;
 901         input [WIDTH*S_WIDTH-1:0] B;
 902         input [S_WIDTH-1:0] S;
 903         output [WIDTH-1:0] Y;
 904
 905         wire [WIDTH-1:0] Y_B;
 906
 907         genvar i, j;
 908         generate
 909                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 910                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 911                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 912                 end:B_AND
 913                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 914                         wire [S_WIDTH-1:0] B_AND_BITS;
 915                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 916                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 917                         end:B_AND_BITS_COLLECT
 918                         assign Y_B[i] = |B_AND_BITS;
 919                 end:B_OR
 920         endgenerate
 921
 922         assign Y = |S ? Y_B : A;
 923 endmodule
 924
 925
 926 // --------------------------------------------------------
 927 // LUTs
 928 // --------------------------------------------------------
 929
 930 `ifndef NOLUT
 931 module \$lut (A, Y);
 932         parameter WIDTH = 1;
 933         parameter LUT = 0;
 934
 935         input [WIDTH-1:0] A;
 936         output Y;
 937
 938         assign Y = LUT[A];
 939 endmodule
 940 `endif
 941