techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$pos $bu0" *)
  43 module simplemap_buffers;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  48 module simplemap_bool_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  53 module simplemap_reduce_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  58 module simplemap_logic_ops;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$slice $concat $mux" *)
  63 module simplemap_various;
  64 endmodule
  65
  66 (* techmap_simplemap *)
  67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  68 module simplemap_registers;
  69 endmodule
  70
  71
  72 // --------------------------------------------------------
  73 // Trivial substitutions
  74 // --------------------------------------------------------
  75
  76 module \$neg (A, Y);
  77         parameter A_SIGNED = 0;
  78         parameter A_WIDTH = 1;
  79         parameter Y_WIDTH = 1;
  80
  81         input [A_WIDTH-1:0] A;
  82         output [Y_WIDTH-1:0] Y;
  83
  84         \$sub #(
  85                 .A_SIGNED(A_SIGNED),
  86                 .B_SIGNED(A_SIGNED),
  87                 .A_WIDTH(1),
  88                 .B_WIDTH(A_WIDTH),
  89                 .Y_WIDTH(Y_WIDTH)
  90         ) _TECHMAP_REPLACE_ (
  91                 .A(1'b0),
  92                 .B(A),
  93                 .Y(Y)
  94         );
  95 endmodule
  96
  97 module \$ge (A, B, Y);
  98         parameter A_SIGNED = 0;
  99         parameter B_SIGNED = 0;
 100         parameter A_WIDTH = 1;
 101         parameter B_WIDTH = 1;
 102         parameter Y_WIDTH = 1;
 103
 104         input [A_WIDTH-1:0] A;
 105         input [B_WIDTH-1:0] B;
 106         output [Y_WIDTH-1:0] Y;
 107
 108         \$le #(
 109                 .A_SIGNED(B_SIGNED),
 110                 .B_SIGNED(A_SIGNED),
 111                 .A_WIDTH(B_WIDTH),
 112                 .B_WIDTH(A_WIDTH),
 113                 .Y_WIDTH(Y_WIDTH)
 114         ) _TECHMAP_REPLACE_ (
 115                 .A(B),
 116                 .B(A),
 117                 .Y(Y)
 118         );
 119 endmodule
 120
 121 module \$gt (A, B, Y);
 122         parameter A_SIGNED = 0;
 123         parameter B_SIGNED = 0;
 124         parameter A_WIDTH = 1;
 125         parameter B_WIDTH = 1;
 126         parameter Y_WIDTH = 1;
 127
 128         input [A_WIDTH-1:0] A;
 129         input [B_WIDTH-1:0] B;
 130         output [Y_WIDTH-1:0] Y;
 131
 132         \$lt #(
 133                 .A_SIGNED(B_SIGNED),
 134                 .B_SIGNED(A_SIGNED),
 135                 .A_WIDTH(B_WIDTH),
 136                 .B_WIDTH(A_WIDTH),
 137                 .Y_WIDTH(Y_WIDTH)
 138         ) _TECHMAP_REPLACE_ (
 139                 .A(B),
 140                 .B(A),
 141                 .Y(Y)
 142         );
 143 endmodule
 144
 145
 146 // --------------------------------------------------------
 147 // Shift operators
 148 // --------------------------------------------------------
 149
 150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 152         parameter A_SIGNED = 0;
 153         parameter B_SIGNED = 0;
 154         parameter A_WIDTH = 1;
 155         parameter B_WIDTH = 1;
 156         parameter Y_WIDTH = 1;
 157
 158         parameter _TECHMAP_CELLTYPE_ = "";
 159         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 160         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 161
 162         input [A_WIDTH-1:0] A;
 163         input [B_WIDTH-1:0] B;
 164         output [Y_WIDTH-1:0] Y;
 165
 166         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 167         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 168
 169         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 170         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 171
 172         integer i;
 173         reg [WIDTH-1:0] buffer;
 174         reg overflow;
 175
 176         always @* begin
 177                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 178                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 179
 180                 for (i = 0; i < BB_WIDTH; i = i+1)
 181                         if (B[i]) begin
 182                                 if (shift_left)
 183                                         buffer = {buffer, (2**i)'b0};
 184                                 else if (2**i < WIDTH)
 185                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 186                                 else
 187                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 188                         end
 189         end
 190
 191         assign Y = buffer;
 192 endmodule
 193
 194 (* techmap_celltype = "$shift $shiftx" *)
 195 module shift_shiftx (A, B, Y);
 196         parameter A_SIGNED = 0;
 197         parameter B_SIGNED = 0;
 198         parameter A_WIDTH = 1;
 199         parameter B_WIDTH = 1;
 200         parameter Y_WIDTH = 1;
 201
 202         input [A_WIDTH-1:0] A;
 203         input [B_WIDTH-1:0] B;
 204         output [Y_WIDTH-1:0] Y;
 205
 206         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 207         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 208
 209         parameter _TECHMAP_CELLTYPE_ = "";
 210         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 211
 212         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 213         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 214
 215         integer i;
 216         reg [WIDTH-1:0] buffer;
 217         reg overflow;
 218
 219         always @* begin
 220                 overflow = 0;
 221                 buffer = {WIDTH{extbit}};
 222                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 223
 224                 if (B_WIDTH > BB_WIDTH) begin
 225                         if (B_SIGNED) begin
 226                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 227                                         if (B[i] != B[BB_WIDTH-1])
 228                                                 overflow = 1;
 229                         end else
 230                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 231                         if (overflow)
 232                                 buffer = {WIDTH{extbit}};
 233                 end
 234
 235                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 236                         if (B[i]) begin
 237                                 if (B_SIGNED && i == BB_WIDTH-1)
 238                                         buffer = {buffer, {2**i{extbit}}};
 239                                 else if (2**i < WIDTH)
 240                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 241                                 else
 242                                         buffer = {WIDTH{extbit}};
 243                         end
 244         end
 245
 246         assign Y = buffer;
 247 endmodule
 248
 249
 250 // --------------------------------------------------------
 251 // ALU Infrastructure
 252 // --------------------------------------------------------
 253
 254 module \$__alu_ripple (A, B, CI, X, Y, CO, CS);
 255         parameter WIDTH = 1;
 256
 257         input [WIDTH-1:0] A, B;
 258         output [WIDTH-1:0] X, Y;
 259
 260         input CI;
 261         output CO, CS;
 262
 263         wire [WIDTH:0] carry;
 264         assign carry[0] = CI;
 265         assign CO = carry[WIDTH];
 266         assign CS = carry[WIDTH-1];
 267
 268         genvar i;
 269         generate
 270                 for (i = 0; i < WIDTH; i = i+1)
 271                 begin:V
 272                         // {x, y} = a + b + c
 273                         wire a, b, c, x, y;
 274                         wire t1, t2, t3;
 275
 276                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(t1) );
 277                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(t2) );
 278                         \$_AND_ gate3 ( .A(t2), .B(c),  .Y(t3) );
 279                         \$_XOR_ gate4 ( .A(t2), .B(c),  .Y(y)  );
 280                         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(x)  );
 281
 282                         assign a = A[i], b = B[i], c = carry[i];
 283                         assign carry[i+1] = x, X[i] = t2, Y[i] = y;
 284                 end
 285         endgenerate
 286 endmodule
 287
 288 module \$__lcu_simple (P, G, CI, CO, PG, GG);
 289         parameter WIDTH = 1;
 290
 291         input [WIDTH-1:0] P, G;
 292         input CI;
 293
 294         output reg [WIDTH:0] CO;
 295         output reg PG, GG;
 296
 297         wire [1023:0] _TECHMAP_DO_ = "proc;;";
 298
 299         integer i, j;
 300         reg [WIDTH-1:0] tmp;
 301
 302         always @* begin
 303                 PG = &P;
 304                 GG = 0;
 305                 for (i = 0; i < WIDTH; i = i+1) begin
 306                         tmp = ~0;
 307                         tmp[i] = G[i];
 308                         for (j = i+1; j < WIDTH; j = j+1)
 309                                 tmp[j] = P[j];
 310                         GG = GG || &tmp[WIDTH-1:i];
 311                 end
 312
 313                 CO[0] = CI;
 314                 for (i = 0; i < WIDTH; i = i+1)
 315                         CO[i+1] = G[i] | (P[i] & CO[i]);
 316         end
 317 endmodule
 318
 319 module \$__lcu (P, G, CI, CO, PG, GG);
 320         parameter WIDTH = 1;
 321
 322         function integer get_group_size;
 323                 begin
 324                         get_group_size = 4;
 325                         while (4 * get_group_size < WIDTH)
 326                                 get_group_size = 4 * get_group_size;
 327                 end
 328         endfunction
 329
 330         input [WIDTH-1:0] P, G;
 331         input CI;
 332
 333         output [WIDTH:0] CO;
 334         output PG, GG;
 335
 336         genvar i;
 337         generate
 338                 if (WIDTH <= 4) begin
 339                         \$__lcu_simple #(.WIDTH(WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO), .PG(PG), .GG(GG));
 340                 end else begin
 341                         localparam GROUP_SIZE = get_group_size();
 342                         localparam GROUPS_NUM = (WIDTH + GROUP_SIZE - 1) / GROUP_SIZE;
 343
 344                         wire [GROUPS_NUM-1:0] groups_p, groups_g;
 345                         wire [GROUPS_NUM:0] groups_ci;
 346
 347                         for (i = 0; i < GROUPS_NUM; i = i+1) begin:V
 348                                 localparam g_size = `MIN(GROUP_SIZE, WIDTH - i*GROUP_SIZE);
 349                                 localparam g_offset = i*GROUP_SIZE;
 350                                 wire [g_size:0] g_co;
 351
 352                                 \$__lcu #(.WIDTH(g_size)) g (.P(P[g_offset +: g_size]), .G(G[g_offset +: g_size]),
 353                                                 .CI(groups_ci[i]), .CO(g_co), .PG(groups_p[i]), .GG(groups_g[i]));
 354                                 assign CO[g_offset+1 +: g_size] = g_co[1 +: g_size];
 355                         end
 356
 357                         \$__lcu_simple #(.WIDTH(GROUPS_NUM)) super_lcu (.P(groups_p), .G(groups_g), .CI(CI), .CO(groups_ci), .PG(PG), .GG(GG));
 358
 359                         assign CO[0] = CI;
 360                 end
 361         endgenerate
 362 endmodule
 363
 364 module \$__alu_lookahead (A, B, CI, X, Y, CO, CS);
 365         parameter WIDTH = 1;
 366
 367         input [WIDTH-1:0] A, B;
 368         output [WIDTH-1:0] X, Y;
 369
 370         input CI;
 371         output CO, CS;
 372
 373         wire [WIDTH-1:0] P, G;
 374         wire [WIDTH:0] C;
 375
 376         assign CO = C[WIDTH];
 377         assign CS = C[WIDTH-1];
 378
 379         genvar i;
 380         generate
 381                 for (i = 0; i < WIDTH; i = i+1)
 382                 begin:V
 383                         wire a, b, c, p, g, y;
 384
 385                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(g) );
 386                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(p) );
 387                         \$_XOR_ gate3 ( .A(p),  .B(c),  .Y(y) );
 388
 389                         assign a = A[i], b = B[i], c = C[i];
 390                         assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
 391                 end
 392         endgenerate
 393
 394         \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
 395 endmodule
 396
 397 module \$__alu (A, B, CI, BI, X, Y, CO, CS);
 398         parameter A_SIGNED = 0;
 399         parameter B_SIGNED = 0;
 400         parameter A_WIDTH = 1;
 401         parameter B_WIDTH = 1;
 402         parameter Y_WIDTH = 1;
 403
 404         input [A_WIDTH-1:0] A;
 405         input [B_WIDTH-1:0] B;
 406         output [Y_WIDTH-1:0] X, Y;
 407
 408         // carry in, sub, carry out, carry sign
 409         input CI, BI;
 410         output CO, CS;
 411
 412         wire [Y_WIDTH-1:0] A_buf, B_buf;
 413         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 414         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 415
 416 `ifdef ALU_RIPPLE
 417         \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
 418 `else
 419         if (Y_WIDTH <= 4) begin
 420                 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
 421         end else begin
 422                 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
 423         end
 424 `endif
 425 endmodule
 426
 427
 428 // --------------------------------------------------------
 429 // ALU Cell Types: Compare, Add, Subtract
 430 // --------------------------------------------------------
 431
 432 `define ALU_COMMONS(_width, _ci, _bi) """
 433         parameter A_SIGNED = 0;
 434         parameter B_SIGNED = 0;
 435         parameter A_WIDTH = 1;
 436         parameter B_WIDTH = 1;
 437         parameter Y_WIDTH = 1;
 438
 439         localparam WIDTH = _width;
 440
 441         input [A_WIDTH-1:0] A;
 442         input [B_WIDTH-1:0] B;
 443         output [Y_WIDTH-1:0] Y;
 444
 445         wire alu_co, alu_cs;
 446         wire [WIDTH-1:0] alu_x, alu_y;
 447
 448         \$__alu #(
 449                 .A_SIGNED(A_SIGNED),
 450                 .B_SIGNED(B_SIGNED),
 451                 .A_WIDTH(A_WIDTH),
 452                 .B_WIDTH(B_WIDTH),
 453                 .Y_WIDTH(WIDTH)
 454         ) alu (
 455                 .A(A),
 456                 .B(B),
 457                 .CI(_ci),
 458                 .BI(_bi),
 459                 .X(alu_x),
 460                 .Y(alu_y),
 461                 .CO(alu_co),
 462                 .CS(alu_cs)
 463         );
 464
 465         wire cf, of, zf, sf;
 466         assign cf = !alu_co;
 467         assign of = alu_co ^ alu_cs;
 468         assign sf = alu_y[WIDTH-1];
 469 """
 470
 471 module \$lt (A, B, Y);
 472         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 473         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 474         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 475 endmodule
 476
 477 module \$le (A, B, Y);
 478         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 479         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 480         assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
 481 endmodule
 482
 483 module \$add (A, B, Y);
 484         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 485         `ALU_COMMONS(Y_WIDTH, 0, 0)
 486         assign Y = alu_y;
 487 endmodule
 488
 489 module \$sub (A, B, Y);
 490         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 491         `ALU_COMMONS(Y_WIDTH, 1, 1)
 492         assign Y = alu_y;
 493 endmodule
 494
 495
 496 // --------------------------------------------------------
 497 // Multiply
 498 // --------------------------------------------------------
 499
 500 module \$__arraymul (A, B, Y);
 501         parameter WIDTH = 8;
 502         input [WIDTH-1:0] A, B;
 503         output [WIDTH-1:0] Y;
 504
 505         wire [1023:0] _TECHMAP_DO_ = "proc;; opt";
 506
 507         integer i;
 508         reg [WIDTH-1:0] x;
 509         reg [2*WIDTH-1:0] y;
 510
 511         function [2*WIDTH-1:0] acc_set;
 512                 input [WIDTH-1:0] value;
 513                 integer k;
 514                 begin
 515                         for (k = 0; k < WIDTH; k = k+1) begin
 516                                 acc_set[2*k +: 2] = value[k];
 517                         end
 518                 end
 519         endfunction
 520
 521         function [2*WIDTH-1:0] acc_add;
 522                 input [2*WIDTH-1:0] old_acc;
 523                 input [WIDTH-1:0] value;
 524                 integer k;
 525                 reg a, b, c;
 526                 begin
 527                         for (k = 0; k < WIDTH; k = k+1) begin
 528                                 a = old_acc[2*k];
 529                                 b = k ? old_acc[2*k-1] : 1'b0;
 530                                 c = value[k];
 531                                 acc_add[2*k] = (a ^ b) ^ c;
 532                                 acc_add[2*k+1] = (a & b) | ((a ^ b) & c);
 533                         end
 534                 end
 535         endfunction
 536
 537         function [WIDTH-1:0] acc_get;
 538                 input [2*WIDTH-1:0] acc;
 539                 integer k;
 540                 begin
 541                         // at the end of the multiplier chain the carry-save accumulator
 542                         // should also have propagated all carries. thus we just need to
 543                         // copy the even bits from the carry accumulator to the output.
 544                         for (k = 0; k < WIDTH; k = k+1) begin
 545                                 acc_get[k] = acc[2*k];
 546                         end
 547                 end
 548         endfunction
 549
 550         always @* begin
 551                 x = B;
 552                 y = acc_set(A[0] ? x : 0);
 553                 for (i = 1; i < WIDTH; i = i+1) begin
 554                         x = {x[WIDTH-2:0], 1'b0};
 555                         y = acc_add(y, A[i] ? x : 0);
 556                 end
 557         end
 558
 559         assign Y = acc_get(y);
 560 endmodule
 561
 562 module \$mul (A, B, Y);
 563         parameter A_SIGNED = 0;
 564         parameter B_SIGNED = 0;
 565         parameter A_WIDTH = 1;
 566         parameter B_WIDTH = 1;
 567         parameter Y_WIDTH = 1;
 568
 569         input [A_WIDTH-1:0] A;
 570         input [B_WIDTH-1:0] B;
 571         output [Y_WIDTH-1:0] Y;
 572
 573         wire [Y_WIDTH-1:0] A_buf, B_buf;
 574         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 575         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 576
 577         \$__arraymul #(
 578                 .WIDTH(Y_WIDTH)
 579         ) arraymul (
 580                 .A(A_buf),
 581                 .B(B_buf),
 582                 .Y(Y)
 583         );
 584 endmodule
 585
 586
 587 // --------------------------------------------------------
 588 // Divide and Modulo
 589 // --------------------------------------------------------
 590
 591 module \$__div_mod_u (A, B, Y, R);
 592         parameter WIDTH = 1;
 593
 594         input [WIDTH-1:0] A, B;
 595         output [WIDTH-1:0] Y, R;
 596
 597         wire [WIDTH*WIDTH-1:0] chaindata;
 598         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 599
 600         genvar i;
 601         generate begin
 602                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 603                         wire [WIDTH-1:0] stage_in;
 604
 605                         if (i == 0) begin:cp
 606                                 assign stage_in = A;
 607                         end else begin:cp
 608                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 609                         end
 610
 611                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 612                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 613                 end
 614         end endgenerate
 615 endmodule
 616
 617 module \$__div_mod (A, B, Y, R);
 618         parameter A_SIGNED = 0;
 619         parameter B_SIGNED = 0;
 620         parameter A_WIDTH = 1;
 621         parameter B_WIDTH = 1;
 622         parameter Y_WIDTH = 1;
 623
 624         localparam WIDTH =
 625                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 626                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 627
 628         input [A_WIDTH-1:0] A;
 629         input [B_WIDTH-1:0] B;
 630         output [Y_WIDTH-1:0] Y, R;
 631
 632         wire [WIDTH-1:0] A_buf, B_buf;
 633         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 634         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 635
 636         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 637         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 638         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 639
 640         \$__div_mod_u #(
 641                 .WIDTH(WIDTH)
 642         ) div_mod_u (
 643                 .A(A_buf_u),
 644                 .B(B_buf_u),
 645                 .Y(Y_u),
 646                 .R(R_u)
 647         );
 648
 649         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 650         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 651 endmodule
 652
 653 module \$div (A, B, Y);
 654         parameter A_SIGNED = 0;
 655         parameter B_SIGNED = 0;
 656         parameter A_WIDTH = 1;
 657         parameter B_WIDTH = 1;
 658         parameter Y_WIDTH = 1;
 659
 660         input [A_WIDTH-1:0] A;
 661         input [B_WIDTH-1:0] B;
 662         output [Y_WIDTH-1:0] Y;
 663
 664         \$__div_mod #(
 665                 .A_SIGNED(A_SIGNED),
 666                 .B_SIGNED(B_SIGNED),
 667                 .A_WIDTH(A_WIDTH),
 668                 .B_WIDTH(B_WIDTH),
 669                 .Y_WIDTH(Y_WIDTH)
 670         ) div_mod (
 671                 .A(A),
 672                 .B(B),
 673                 .Y(Y)
 674         );
 675 endmodule
 676
 677 module \$mod (A, B, Y);
 678         parameter A_SIGNED = 0;
 679         parameter B_SIGNED = 0;
 680         parameter A_WIDTH = 1;
 681         parameter B_WIDTH = 1;
 682         parameter Y_WIDTH = 1;
 683
 684         input [A_WIDTH-1:0] A;
 685         input [B_WIDTH-1:0] B;
 686         output [Y_WIDTH-1:0] Y;
 687
 688         \$__div_mod #(
 689                 .A_SIGNED(A_SIGNED),
 690                 .B_SIGNED(B_SIGNED),
 691                 .A_WIDTH(A_WIDTH),
 692                 .B_WIDTH(B_WIDTH),
 693                 .Y_WIDTH(Y_WIDTH)
 694         ) div_mod (
 695                 .A(A),
 696                 .B(B),
 697                 .R(Y)
 698         );
 699 endmodule
 700
 701
 702 // --------------------------------------------------------
 703 // Power
 704 // --------------------------------------------------------
 705
 706 module \$pow (A, B, Y);
 707         parameter A_SIGNED = 0;
 708         parameter B_SIGNED = 0;
 709         parameter A_WIDTH = 1;
 710         parameter B_WIDTH = 1;
 711         parameter Y_WIDTH = 1;
 712
 713         input [A_WIDTH-1:0] A;
 714         input [B_WIDTH-1:0] B;
 715         output [Y_WIDTH-1:0] Y;
 716
 717         wire _TECHMAP_FAIL_ = 1;
 718 endmodule
 719
 720
 721 // --------------------------------------------------------
 722 // Equal and Not-Equal
 723 // --------------------------------------------------------
 724
 725 module \$eq (A, B, Y);
 726         parameter A_SIGNED = 0;
 727         parameter B_SIGNED = 0;
 728         parameter A_WIDTH = 1;
 729         parameter B_WIDTH = 1;
 730         parameter Y_WIDTH = 1;
 731
 732         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 733
 734         input [A_WIDTH-1:0] A;
 735         input [B_WIDTH-1:0] B;
 736         output [Y_WIDTH-1:0] Y;
 737
 738         wire carry, carry_sign;
 739         wire [WIDTH-1:0] A_buf, B_buf;
 740         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 741         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 742
 743         assign Y = ~|(A_buf ^ B_buf);
 744 endmodule
 745
 746 module \$ne (A, B, Y);
 747         parameter A_SIGNED = 0;
 748         parameter B_SIGNED = 0;
 749         parameter A_WIDTH = 1;
 750         parameter B_WIDTH = 1;
 751         parameter Y_WIDTH = 1;
 752
 753         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 754
 755         input [A_WIDTH-1:0] A;
 756         input [B_WIDTH-1:0] B;
 757         output [Y_WIDTH-1:0] Y;
 758
 759         wire carry, carry_sign;
 760         wire [WIDTH-1:0] A_buf, B_buf;
 761         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 762         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 763
 764         assign Y = |(A_buf ^ B_buf);
 765 endmodule
 766
 767 module \$eqx (A, B, Y);
 768         parameter A_SIGNED = 0;
 769         parameter B_SIGNED = 0;
 770         parameter A_WIDTH = 1;
 771         parameter B_WIDTH = 1;
 772         parameter Y_WIDTH = 1;
 773
 774         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 775
 776         input [A_WIDTH-1:0] A;
 777         input [B_WIDTH-1:0] B;
 778         output [Y_WIDTH-1:0] Y;
 779
 780         wire carry, carry_sign;
 781         wire [WIDTH-1:0] A_buf, B_buf;
 782         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 783         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 784
 785         assign Y = ~|(A_buf ^ B_buf);
 786 endmodule
 787
 788 module \$nex (A, B, Y);
 789         parameter A_SIGNED = 0;
 790         parameter B_SIGNED = 0;
 791         parameter A_WIDTH = 1;
 792         parameter B_WIDTH = 1;
 793         parameter Y_WIDTH = 1;
 794
 795         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 796
 797         input [A_WIDTH-1:0] A;
 798         input [B_WIDTH-1:0] B;
 799         output [Y_WIDTH-1:0] Y;
 800
 801         wire carry, carry_sign;
 802         wire [WIDTH-1:0] A_buf, B_buf;
 803         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 804         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 805
 806         assign Y = |(A_buf ^ B_buf);
 807 endmodule
 808
 809
 810 // --------------------------------------------------------
 811 // Parallel Multiplexers
 812 // --------------------------------------------------------
 813
 814 module \$pmux (A, B, S, Y);
 815         parameter WIDTH = 1;
 816         parameter S_WIDTH = 1;
 817
 818         input [WIDTH-1:0] A;
 819         input [WIDTH*S_WIDTH-1:0] B;
 820         input [S_WIDTH-1:0] S;
 821         output [WIDTH-1:0] Y;
 822
 823         wire [WIDTH-1:0] Y_B;
 824
 825         genvar i, j;
 826         generate
 827                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 828                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 829                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 830                 end:B_AND
 831                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 832                         wire [S_WIDTH-1:0] B_AND_BITS;
 833                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 834                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 835                         end:B_AND_BITS_COLLECT
 836                         assign Y_B[i] = |B_AND_BITS;
 837                 end:B_OR
 838         endgenerate
 839
 840         assign Y = |S ? Y_B : A;
 841 endmodule
 842