techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_INV_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$pos $bu0" *)
  43 module simplemap_buffers;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  48 module simplemap_bool_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  53 module simplemap_reduce_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  58 module simplemap_logic_ops;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$slice $concat $mux" *)
  63 module simplemap_various;
  64 endmodule
  65
  66 (* techmap_simplemap *)
  67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  68 module simplemap_registers;
  69 endmodule
  70
  71
  72 // --------------------------------------------------------
  73 // Trivial substitutions
  74 // --------------------------------------------------------
  75
  76 module \$neg (A, Y);
  77         parameter A_SIGNED = 0;
  78         parameter A_WIDTH = 1;
  79         parameter Y_WIDTH = 1;
  80
  81         input [A_WIDTH-1:0] A;
  82         output [Y_WIDTH-1:0] Y;
  83
  84         \$sub #(
  85                 .A_SIGNED(A_SIGNED),
  86                 .B_SIGNED(A_SIGNED),
  87                 .A_WIDTH(1),
  88                 .B_WIDTH(A_WIDTH),
  89                 .Y_WIDTH(Y_WIDTH)
  90         ) _TECHMAP_REPLACE_ (
  91                 .A(1'b0),
  92                 .B(A),
  93                 .Y(Y)
  94         );
  95 endmodule
  96
  97 module \$ge (A, B, Y);
  98         parameter A_SIGNED = 0;
  99         parameter B_SIGNED = 0;
 100         parameter A_WIDTH = 1;
 101         parameter B_WIDTH = 1;
 102         parameter Y_WIDTH = 1;
 103
 104         input [A_WIDTH-1:0] A;
 105         input [B_WIDTH-1:0] B;
 106         output [Y_WIDTH-1:0] Y;
 107
 108         \$le #(
 109                 .A_SIGNED(B_SIGNED),
 110                 .B_SIGNED(A_SIGNED),
 111                 .A_WIDTH(B_WIDTH),
 112                 .B_WIDTH(A_WIDTH),
 113                 .Y_WIDTH(Y_WIDTH)
 114         ) _TECHMAP_REPLACE_ (
 115                 .A(B),
 116                 .B(A),
 117                 .Y(Y)
 118         );
 119 endmodule
 120
 121 module \$gt (A, B, Y);
 122         parameter A_SIGNED = 0;
 123         parameter B_SIGNED = 0;
 124         parameter A_WIDTH = 1;
 125         parameter B_WIDTH = 1;
 126         parameter Y_WIDTH = 1;
 127
 128         input [A_WIDTH-1:0] A;
 129         input [B_WIDTH-1:0] B;
 130         output [Y_WIDTH-1:0] Y;
 131
 132         \$lt #(
 133                 .A_SIGNED(B_SIGNED),
 134                 .B_SIGNED(A_SIGNED),
 135                 .A_WIDTH(B_WIDTH),
 136                 .B_WIDTH(A_WIDTH),
 137                 .Y_WIDTH(Y_WIDTH)
 138         ) _TECHMAP_REPLACE_ (
 139                 .A(B),
 140                 .B(A),
 141                 .Y(Y)
 142         );
 143 endmodule
 144
 145
 146 // --------------------------------------------------------
 147 // Shift operators
 148 // --------------------------------------------------------
 149
 150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 152         parameter A_SIGNED = 0;
 153         parameter B_SIGNED = 0;
 154         parameter A_WIDTH = 1;
 155         parameter B_WIDTH = 1;
 156         parameter Y_WIDTH = 1;
 157
 158         parameter _TECHMAP_CELLTYPE_ = "";
 159         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 160         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 161
 162         input [A_WIDTH-1:0] A;
 163         input [B_WIDTH-1:0] B;
 164         output [Y_WIDTH-1:0] Y;
 165
 166         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 167         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 168
 169         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 170         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 171
 172         integer i;
 173         reg [WIDTH-1:0] buffer;
 174         reg overflow;
 175
 176         always @* begin
 177                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 178                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 179
 180                 for (i = 0; i < BB_WIDTH; i = i+1)
 181                         if (B[i]) begin
 182                                 if (shift_left)
 183                                         buffer = {buffer, (2**i)'b0};
 184                                 else if (2**i < WIDTH)
 185                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 186                                 else
 187                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 188                         end
 189         end
 190
 191         assign Y = buffer;
 192 endmodule
 193
 194 (* techmap_celltype = "$shift $shiftx" *)
 195 module shift_shiftx (A, B, Y);
 196         parameter A_SIGNED = 0;
 197         parameter B_SIGNED = 0;
 198         parameter A_WIDTH = 1;
 199         parameter B_WIDTH = 1;
 200         parameter Y_WIDTH = 1;
 201
 202         input [A_WIDTH-1:0] A;
 203         input [B_WIDTH-1:0] B;
 204         output [Y_WIDTH-1:0] Y;
 205
 206         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 207         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 208
 209         parameter _TECHMAP_CELLTYPE_ = "";
 210         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 211
 212         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 213         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 214
 215         integer i;
 216         reg [WIDTH-1:0] buffer;
 217         reg overflow;
 218
 219         always @* begin
 220                 overflow = 0;
 221                 buffer = {WIDTH{extbit}};
 222                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 223
 224                 if (B_WIDTH > BB_WIDTH) begin
 225                         if (B_SIGNED) begin
 226                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 227                                         if (B[i] != B[BB_WIDTH-1])
 228                                                 overflow = 1;
 229                         end else
 230                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 231                         if (overflow)
 232                                 buffer = {WIDTH{extbit}};
 233                 end
 234
 235                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 236                         if (B[i]) begin
 237                                 if (B_SIGNED && i == BB_WIDTH-1)
 238                                         buffer = {buffer, {2**i{extbit}}};
 239                                 else if (2**i < WIDTH)
 240                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 241                                 else
 242                                         buffer = {WIDTH{extbit}};
 243                         end
 244         end
 245
 246         assign Y = buffer;
 247 endmodule
 248
 249
 250 // --------------------------------------------------------
 251 // ALU Infrastructure
 252 // --------------------------------------------------------
 253
 254 module \$__alu_ripple (A, B, CI, Y, CO, CS);
 255         parameter WIDTH = 1;
 256
 257         input [WIDTH-1:0] A, B;
 258         output [WIDTH-1:0] Y;
 259
 260         input CI;
 261         output CO, CS;
 262
 263         wire [WIDTH:0] carry;
 264         assign carry[0] = CI;
 265         assign CO = carry[WIDTH];
 266         assign CS = carry[WIDTH-1];
 267
 268         genvar i;
 269         generate
 270                 for (i = 0; i < WIDTH; i = i + 1)
 271                 begin:V
 272                         // {x, y} = a + b + c
 273                         wire a, b, c, x, y;
 274                         wire t1, t2, t3;
 275
 276                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(t1) );
 277                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(t2) );
 278                         \$_AND_ gate3 ( .A(t2), .B(c),  .Y(t3) );
 279                         \$_XOR_ gate4 ( .A(t2), .B(c),  .Y(y)  );
 280                         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(x)  );
 281
 282                         assign a = A[i], b = B[i], c = carry[i];
 283                         assign carry[i+1] = x, Y[i] = y;
 284                 end
 285         endgenerate
 286 endmodule
 287
 288 module \$__lcu (P, G, CI, CO, PG, GG);
 289         parameter WIDTH = 1;
 290
 291         input [WIDTH-1:0] P, G;
 292         input CI;
 293
 294         output [WIDTH:0] CO;
 295         output PG, GG;
 296
 297         assign CO[0] = CI;
 298         assign PG = 'bx, GG = 'bx;
 299
 300         genvar i;
 301         generate
 302                 // TBD: Actually implement a LCU topology
 303                 for (i = 0; i < WIDTH; i = i + 1)
 304                         assign CO[i+1] = G[i] | (P[i] & CO[i]);
 305         endgenerate
 306 endmodule
 307
 308 module \$__alu_lookahead (A, B, CI, Y, CO, CS);
 309         parameter WIDTH = 1;
 310
 311         input [WIDTH-1:0] A, B;
 312         output [WIDTH-1:0] Y;
 313
 314         input CI;
 315         output CO, CS;
 316
 317         wire [WIDTH-1:0] P, G;
 318         wire [WIDTH:0] C;
 319
 320         assign CO = C[WIDTH];
 321         assign CS = C[WIDTH-1];
 322
 323         genvar i;
 324         generate
 325                 for (i = 0; i < WIDTH; i = i + 1)
 326                 begin:V
 327                         wire a, b, c, p, g, y;
 328
 329                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(g) );
 330                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(p) );
 331                         \$_XOR_ gate3 ( .A(p),  .B(c),  .Y(y) );
 332
 333                         assign a = A[i], b = B[i], c = C[i];
 334                         assign P[i] = p, G[i] = g, Y[i] = y;
 335                 end
 336         endgenerate
 337
 338         \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
 339 endmodule
 340
 341 module \$__alu (A, B, CI, S, Y, CO, CS);
 342         parameter A_SIGNED = 0;
 343         parameter B_SIGNED = 0;
 344         parameter A_WIDTH = 1;
 345         parameter B_WIDTH = 1;
 346         parameter Y_WIDTH = 1;
 347
 348         input [A_WIDTH-1:0] A;
 349         input [B_WIDTH-1:0] B;
 350         output [Y_WIDTH-1:0] Y;
 351
 352         // carry in, sub, carry out, carry sign
 353         input CI, S;
 354         output CO, CS;
 355
 356         wire [Y_WIDTH-1:0] A_buf, B_buf;
 357         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 358         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 359
 360 `ifdef ALU_RIPPLE
 361         \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
 362 `else
 363         if (Y_WIDTH <= 4) begin
 364                 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
 365         end else begin
 366                 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(S ? ~B_buf : B_buf), .CI(CI), .Y(Y), .CO(CO), .CS(CS));
 367         end
 368 `endif
 369 endmodule
 370
 371 `define ALU_COMMONS(_width, _ci, _s) """
 372         parameter A_SIGNED = 0;
 373         parameter B_SIGNED = 0;
 374         parameter A_WIDTH = 1;
 375         parameter B_WIDTH = 1;
 376         parameter Y_WIDTH = 1;
 377
 378         localparam WIDTH = _width;
 379
 380         input [A_WIDTH-1:0] A;
 381         input [B_WIDTH-1:0] B;
 382         output [Y_WIDTH-1:0] Y;
 383
 384         wire alu_co, alu_cs;
 385         wire [WIDTH-1:0] alu_y;
 386
 387         \$__alu #(
 388                 .A_SIGNED(A_SIGNED),
 389                 .B_SIGNED(B_SIGNED),
 390                 .A_WIDTH(A_WIDTH),
 391                 .B_WIDTH(B_WIDTH),
 392                 .Y_WIDTH(WIDTH)
 393         ) alu (
 394                 .A(A),
 395                 .B(B),
 396                 .CI(_ci),
 397                 .S(_s),
 398                 .Y(alu_y),
 399                 .CO(alu_co),
 400                 .CS(alu_cs)
 401         );
 402
 403         wire cf, of, zf, sf;
 404         assign cf = !alu_co;
 405         assign of = alu_co ^ alu_cs;
 406         assign zf = ~|alu_y;
 407         assign sf = alu_y[WIDTH-1];
 408 """
 409
 410
 411 // --------------------------------------------------------
 412 // Compare cells
 413 // --------------------------------------------------------
 414
 415 module \$lt (A, B, Y);
 416         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 417         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 418         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 419 endmodule
 420
 421 module \$le (A, B, Y);
 422         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 423         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 424         assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
 425 endmodule
 426
 427
 428 // --------------------------------------------------------
 429 // Add and Subtract
 430 // --------------------------------------------------------
 431
 432 module \$add (A, B, Y);
 433         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 434         `ALU_COMMONS(Y_WIDTH, 0, 0)
 435         assign Y = alu_y;
 436 endmodule
 437
 438 module \$sub (A, B, Y);
 439         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 440         `ALU_COMMONS(Y_WIDTH, 1, 1)
 441         assign Y = alu_y;
 442 endmodule
 443
 444
 445 // --------------------------------------------------------
 446 // Multiply
 447 // --------------------------------------------------------
 448
 449 module \$__arraymul (A, B, Y);
 450         parameter WIDTH = 8;
 451         input [WIDTH-1:0] A, B;
 452         output [WIDTH-1:0] Y;
 453
 454         wire [WIDTH*WIDTH-1:0] partials;
 455
 456         genvar i;
 457         assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
 458         generate for (i = 1; i < WIDTH; i = i+1) begin:gen
 459                 assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
 460         end endgenerate
 461
 462         assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
 463 endmodule
 464
 465 module \$mul (A, B, Y);
 466         parameter A_SIGNED = 0;
 467         parameter B_SIGNED = 0;
 468         parameter A_WIDTH = 1;
 469         parameter B_WIDTH = 1;
 470         parameter Y_WIDTH = 1;
 471
 472         input [A_WIDTH-1:0] A;
 473         input [B_WIDTH-1:0] B;
 474         output [Y_WIDTH-1:0] Y;
 475
 476         wire [Y_WIDTH-1:0] A_buf, B_buf;
 477         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 478         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 479
 480         \$__arraymul #(
 481                 .WIDTH(Y_WIDTH)
 482         ) arraymul (
 483                 .A(A_buf),
 484                 .B(B_buf),
 485                 .Y(Y)
 486         );
 487 endmodule
 488
 489
 490 // --------------------------------------------------------
 491 // Divide and Modulo
 492 // --------------------------------------------------------
 493
 494 module \$__div_mod_u (A, B, Y, R);
 495         parameter WIDTH = 1;
 496
 497         input [WIDTH-1:0] A, B;
 498         output [WIDTH-1:0] Y, R;
 499
 500         wire [WIDTH*WIDTH-1:0] chaindata;
 501         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 502
 503         genvar i;
 504         generate begin
 505                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 506                         wire [WIDTH-1:0] stage_in;
 507
 508                         if (i == 0) begin:cp
 509                                 assign stage_in = A;
 510                         end else begin:cp
 511                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 512                         end
 513
 514                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 515                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 516                 end
 517         end endgenerate
 518 endmodule
 519
 520 module \$__div_mod (A, B, Y, R);
 521         parameter A_SIGNED = 0;
 522         parameter B_SIGNED = 0;
 523         parameter A_WIDTH = 1;
 524         parameter B_WIDTH = 1;
 525         parameter Y_WIDTH = 1;
 526
 527         localparam WIDTH =
 528                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 529                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 530
 531         input [A_WIDTH-1:0] A;
 532         input [B_WIDTH-1:0] B;
 533         output [Y_WIDTH-1:0] Y, R;
 534
 535         wire [WIDTH-1:0] A_buf, B_buf;
 536         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 537         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 538
 539         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 540         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 541         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 542
 543         \$__div_mod_u #(
 544                 .WIDTH(WIDTH)
 545         ) div_mod_u (
 546                 .A(A_buf_u),
 547                 .B(B_buf_u),
 548                 .Y(Y_u),
 549                 .R(R_u)
 550         );
 551
 552         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 553         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 554 endmodule
 555
 556 module \$div (A, B, Y);
 557         parameter A_SIGNED = 0;
 558         parameter B_SIGNED = 0;
 559         parameter A_WIDTH = 1;
 560         parameter B_WIDTH = 1;
 561         parameter Y_WIDTH = 1;
 562
 563         input [A_WIDTH-1:0] A;
 564         input [B_WIDTH-1:0] B;
 565         output [Y_WIDTH-1:0] Y;
 566
 567         \$__div_mod #(
 568                 .A_SIGNED(A_SIGNED),
 569                 .B_SIGNED(B_SIGNED),
 570                 .A_WIDTH(A_WIDTH),
 571                 .B_WIDTH(B_WIDTH),
 572                 .Y_WIDTH(Y_WIDTH)
 573         ) div_mod (
 574                 .A(A),
 575                 .B(B),
 576                 .Y(Y)
 577         );
 578 endmodule
 579
 580 module \$mod (A, B, Y);
 581         parameter A_SIGNED = 0;
 582         parameter B_SIGNED = 0;
 583         parameter A_WIDTH = 1;
 584         parameter B_WIDTH = 1;
 585         parameter Y_WIDTH = 1;
 586
 587         input [A_WIDTH-1:0] A;
 588         input [B_WIDTH-1:0] B;
 589         output [Y_WIDTH-1:0] Y;
 590
 591         \$__div_mod #(
 592                 .A_SIGNED(A_SIGNED),
 593                 .B_SIGNED(B_SIGNED),
 594                 .A_WIDTH(A_WIDTH),
 595                 .B_WIDTH(B_WIDTH),
 596                 .Y_WIDTH(Y_WIDTH)
 597         ) div_mod (
 598                 .A(A),
 599                 .B(B),
 600                 .R(Y)
 601         );
 602 endmodule
 603
 604
 605 // --------------------------------------------------------
 606 // Power
 607 // --------------------------------------------------------
 608
 609 module \$pow (A, B, Y);
 610         parameter A_SIGNED = 0;
 611         parameter B_SIGNED = 0;
 612         parameter A_WIDTH = 1;
 613         parameter B_WIDTH = 1;
 614         parameter Y_WIDTH = 1;
 615
 616         input [A_WIDTH-1:0] A;
 617         input [B_WIDTH-1:0] B;
 618         output [Y_WIDTH-1:0] Y;
 619
 620         wire _TECHMAP_FAIL_ = 1;
 621 endmodule
 622
 623
 624 // --------------------------------------------------------
 625 // Equal and Not-Equal
 626 // --------------------------------------------------------
 627
 628 module \$eq (A, B, Y);
 629         parameter A_SIGNED = 0;
 630         parameter B_SIGNED = 0;
 631         parameter A_WIDTH = 1;
 632         parameter B_WIDTH = 1;
 633         parameter Y_WIDTH = 1;
 634
 635         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 636
 637         input [A_WIDTH-1:0] A;
 638         input [B_WIDTH-1:0] B;
 639         output [Y_WIDTH-1:0] Y;
 640
 641         wire carry, carry_sign;
 642         wire [WIDTH-1:0] A_buf, B_buf;
 643         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 644         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 645
 646         assign Y = ~|(A_buf ^ B_buf);
 647 endmodule
 648
 649 module \$ne (A, B, Y);
 650         parameter A_SIGNED = 0;
 651         parameter B_SIGNED = 0;
 652         parameter A_WIDTH = 1;
 653         parameter B_WIDTH = 1;
 654         parameter Y_WIDTH = 1;
 655
 656         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 657
 658         input [A_WIDTH-1:0] A;
 659         input [B_WIDTH-1:0] B;
 660         output [Y_WIDTH-1:0] Y;
 661
 662         wire carry, carry_sign;
 663         wire [WIDTH-1:0] A_buf, B_buf;
 664         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 665         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 666
 667         assign Y = |(A_buf ^ B_buf);
 668 endmodule
 669
 670 module \$eqx (A, B, Y);
 671         parameter A_SIGNED = 0;
 672         parameter B_SIGNED = 0;
 673         parameter A_WIDTH = 1;
 674         parameter B_WIDTH = 1;
 675         parameter Y_WIDTH = 1;
 676
 677         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 678
 679         input [A_WIDTH-1:0] A;
 680         input [B_WIDTH-1:0] B;
 681         output [Y_WIDTH-1:0] Y;
 682
 683         wire carry, carry_sign;
 684         wire [WIDTH-1:0] A_buf, B_buf;
 685         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 686         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 687
 688         assign Y = ~|(A_buf ^ B_buf);
 689 endmodule
 690
 691 module \$nex (A, B, Y);
 692         parameter A_SIGNED = 0;
 693         parameter B_SIGNED = 0;
 694         parameter A_WIDTH = 1;
 695         parameter B_WIDTH = 1;
 696         parameter Y_WIDTH = 1;
 697
 698         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 699
 700         input [A_WIDTH-1:0] A;
 701         input [B_WIDTH-1:0] B;
 702         output [Y_WIDTH-1:0] Y;
 703
 704         wire carry, carry_sign;
 705         wire [WIDTH-1:0] A_buf, B_buf;
 706         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 707         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 708
 709         assign Y = |(A_buf ^ B_buf);
 710 endmodule
 711
 712
 713 // --------------------------------------------------------
 714 // Parallel Multiplexers
 715 // --------------------------------------------------------
 716
 717 module \$pmux (A, B, S, Y);
 718         parameter WIDTH = 1;
 719         parameter S_WIDTH = 1;
 720
 721         input [WIDTH-1:0] A;
 722         input [WIDTH*S_WIDTH-1:0] B;
 723         input [S_WIDTH-1:0] S;
 724         output [WIDTH-1:0] Y;
 725
 726         wire [WIDTH-1:0] Y_B;
 727
 728         genvar i, j;
 729         generate
 730                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 731                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 732                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 733                 end:B_AND
 734                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 735                         wire [S_WIDTH-1:0] B_AND_BITS;
 736                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 737                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 738                         end:B_AND_BITS_COLLECT
 739                         assign Y_B[i] = |B_AND_BITS;
 740                 end:B_OR
 741         endgenerate
 742
 743         assign Y = |S ? Y_B : A;
 744 endmodule
 745
 746 module \$safe_pmux (A, B, S, Y);
 747         parameter WIDTH = 1;
 748         parameter S_WIDTH = 1;
 749
 750         input [WIDTH-1:0] A;
 751         input [WIDTH*S_WIDTH-1:0] B;
 752         input [S_WIDTH-1:0] S;
 753         output [WIDTH-1:0] Y;
 754
 755         wire [S_WIDTH-1:0] status_found_first;
 756         wire [S_WIDTH-1:0] status_found_second;
 757
 758         genvar i;
 759         generate
 760                 for (i = 0; i < S_WIDTH; i = i + 1) begin:GEN1
 761                         wire pre_first;
 762                         if (i > 0) begin:GEN2
 763                                 assign pre_first = status_found_first[i-1];
 764                         end:GEN2 else begin:GEN3
 765                                 assign pre_first = 0;
 766                         end:GEN3
 767                         assign status_found_first[i] = pre_first | S[i];
 768                         assign status_found_second[i] = pre_first & S[i];
 769                 end:GEN1
 770         endgenerate
 771
 772         \$pmux #(
 773                 .WIDTH(WIDTH),
 774                 .S_WIDTH(S_WIDTH)
 775         ) pmux_cell (
 776                 .A(A),
 777                 .B(B),
 778                 .S(S & {S_WIDTH{~|status_found_second}}),
 779                 .Y(Y)
 780         );
 781 endmodule
 782