2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
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10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * The internal logic cell technology mapper.
22 * This Verilog library contains the mapping of internal cells (e.g. $not with
23 * variable bit width) to the internal logic cells (such as the single bit $_NOT_
24 * gate). Usually this logic network is then mapped to the actual technology
25 * using e.g. the "abc" pass.
27 * Note that this library does not map $mem cells. They must be mapped to logic
28 * and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
29 * which is of course highly recommended for larger memories.)
33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
37 // --------------------------------------------------------
38 // Use simplemap for trivial cell types
39 // --------------------------------------------------------
41 (* techmap_simplemap *)
42 (* techmap_celltype = "$not $and $or $xor $xnor" *)
43 module _90_simplemap_bool_ops;
46 (* techmap_simplemap *)
47 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
48 module _90_simplemap_reduce_ops;
51 (* techmap_simplemap *)
52 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
53 module _90_simplemap_logic_ops;
56 (* techmap_simplemap *)
57 (* techmap_celltype = "$eq $eqx $ne $nex" *)
58 module _90_simplemap_compare_ops;
61 (* techmap_simplemap *)
62 (* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux" *)
63 module _90_simplemap_various;
66 (* techmap_simplemap *)
67 (* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
68 module _90_simplemap_registers;
72 // --------------------------------------------------------
74 // --------------------------------------------------------
76 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
77 module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
78 parameter A_SIGNED = 0;
79 parameter B_SIGNED = 0;
80 parameter A_WIDTH = 1;
81 parameter B_WIDTH = 1;
82 parameter Y_WIDTH = 1;
84 parameter _TECHMAP_CELLTYPE_ = "";
85 localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
86 localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
89 input [A_WIDTH-1:0] A;
91 input [B_WIDTH-1:0] B;
93 output [Y_WIDTH-1:0] Y;
95 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
96 localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
98 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
99 wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
103 reg [WIDTH-1:0] buffer;
107 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
108 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
110 for (i = 0; i < BB_WIDTH; i = i+1)
113 buffer = {buffer, (2**i)'b0};
114 else if (2**i < WIDTH)
115 buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
117 buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
124 (* techmap_celltype = "$shift $shiftx" *)
125 module _90_shift_shiftx (A, B, Y);
126 parameter A_SIGNED = 0;
127 parameter B_SIGNED = 0;
128 parameter A_WIDTH = 1;
129 parameter B_WIDTH = 1;
130 parameter Y_WIDTH = 1;
133 input [A_WIDTH-1:0] A;
135 input [B_WIDTH-1:0] B;
137 output [Y_WIDTH-1:0] Y;
139 parameter _TECHMAP_CELLTYPE_ = "";
140 parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
141 parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
143 localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
144 wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
146 localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
147 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
149 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
150 wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
154 reg [WIDTH-1:0] buffer;
159 buffer = {WIDTH{extbit}};
160 buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
161 buffer[A_WIDTH-1:0] = A;
163 if (B_WIDTH > BB_WIDTH) begin
165 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
166 if (B[i] != B[BB_WIDTH-1])
169 overflow = |B[B_WIDTH-1:BB_WIDTH];
171 buffer = {WIDTH{extbit}};
174 if (B_SIGNED && B[BB_WIDTH-1])
175 buffer = {buffer, {2**(BB_WIDTH-1){extbit}}};
177 for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)
180 buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
182 buffer = {WIDTH{extbit}};
189 // --------------------------------------------------------
190 // Arithmetic operators
191 // --------------------------------------------------------
193 (* techmap_celltype = "$fa" *)
194 module _90_fa (A, B, C, X, Y);
198 input [WIDTH-1:0] A, B, C;
200 output [WIDTH-1:0] X, Y;
203 wire [WIDTH-1:0] t1, t2, t3;
205 assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
206 assign Y = t1 ^ C, X = t2 | t3;
209 (* techmap_celltype = "$lcu" *)
210 module _90_lcu (P, G, CI, CO);
214 input [WIDTH-1:0] P, G;
218 output [WIDTH-1:0] CO;
222 reg [WIDTH-1:0] p, g;
224 wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
230 // in almost all cases CI will be constant zero
231 g[0] = g[0] | (p[0] & CI);
233 // [[CITE]] Brent Kung Adder
234 // R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders",
235 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
238 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
239 for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
240 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
241 p[j] = p[j] & p[j - 2**(i-1)];
246 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
247 for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
248 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
249 p[j] = p[j] & p[j - 2**(i-1)];
257 (* techmap_celltype = "$alu" *)
258 module _90_alu (A, B, CI, BI, X, Y, CO);
259 parameter A_SIGNED = 0;
260 parameter B_SIGNED = 0;
261 parameter A_WIDTH = 1;
262 parameter B_WIDTH = 1;
263 parameter Y_WIDTH = 1;
266 input [A_WIDTH-1:0] A;
268 input [B_WIDTH-1:0] B;
270 output [Y_WIDTH-1:0] X, Y;
274 output [Y_WIDTH-1:0] CO;
277 wire [Y_WIDTH-1:0] AA = A_buf;
279 wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
282 wire [Y_WIDTH-1:0] A_buf, B_buf;
283 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
284 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
286 \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
289 assign Y = X ^ {CO, CI};
292 (* techmap_maccmap *)
293 (* techmap_celltype = "$macc" *)
297 (* techmap_wrap = "alumacc" *)
298 (* techmap_celltype = "$lt $le $ge $gt $add $sub $neg $mul" *)
303 // --------------------------------------------------------
305 // --------------------------------------------------------
307 module \$__div_mod_u (A, B, Y, R);
311 input [WIDTH-1:0] A, B;
313 output [WIDTH-1:0] Y, R;
316 wire [WIDTH*WIDTH-1:0] chaindata;
317 assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
321 for (i = 0; i < WIDTH; i=i+1) begin:stage
323 wire [WIDTH-1:0] stage_in;
328 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
331 assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
332 assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
337 // truncating signed division/modulo
338 module \$__div_mod_trunc (A, B, Y, R);
339 parameter A_SIGNED = 0;
340 parameter B_SIGNED = 0;
341 parameter A_WIDTH = 1;
342 parameter B_WIDTH = 1;
343 parameter Y_WIDTH = 1;
346 A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
347 B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
350 input [A_WIDTH-1:0] A;
352 input [B_WIDTH-1:0] B;
354 output [Y_WIDTH-1:0] Y, R;
357 wire [WIDTH-1:0] A_buf, B_buf;
358 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
359 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
362 wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
363 assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
364 assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
375 assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
376 assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
379 (* techmap_celltype = "$div" *)
380 module _90_div (A, B, Y);
381 parameter A_SIGNED = 0;
382 parameter B_SIGNED = 0;
383 parameter A_WIDTH = 1;
384 parameter B_WIDTH = 1;
385 parameter Y_WIDTH = 1;
388 input [A_WIDTH-1:0] A;
390 input [B_WIDTH-1:0] B;
392 output [Y_WIDTH-1:0] Y;
407 (* techmap_celltype = "$mod" *)
408 module _90_mod (A, B, Y);
409 parameter A_SIGNED = 0;
410 parameter B_SIGNED = 0;
411 parameter A_WIDTH = 1;
412 parameter B_WIDTH = 1;
413 parameter Y_WIDTH = 1;
416 input [A_WIDTH-1:0] A;
418 input [B_WIDTH-1:0] B;
420 output [Y_WIDTH-1:0] Y;
435 // flooring signed division/modulo
436 module \$__div_mod_floor (A, B, Y, R);
437 parameter A_SIGNED = 0;
438 parameter B_SIGNED = 0;
439 parameter A_WIDTH = 1;
440 parameter B_WIDTH = 1;
441 parameter Y_WIDTH = 1;
444 A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
445 B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
447 input [A_WIDTH-1:0] A;
448 input [B_WIDTH-1:0] B;
449 output [Y_WIDTH-1:0] Y, R;
451 wire [WIDTH-1:0] A_buf, B_buf;
452 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
453 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
455 wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;
456 assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
457 assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
468 // For negative results, if there was a remainder, subtract one to turn
469 // the round towards 0 into a round towards -inf
470 assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;
473 assign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
474 // Flooring modulo differs from truncating modulo only if it is nonzero and
475 // A and B have different signs - then `floor - trunc = B`
476 assign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;
479 (* techmap_celltype = "$divfloor" *)
480 module _90_divfloor (A, B, Y);
481 parameter A_SIGNED = 0;
482 parameter B_SIGNED = 0;
483 parameter A_WIDTH = 1;
484 parameter B_WIDTH = 1;
485 parameter Y_WIDTH = 1;
488 input [A_WIDTH-1:0] A;
490 input [B_WIDTH-1:0] B;
492 output [Y_WIDTH-1:0] Y;
507 (* techmap_celltype = "$modfloor" *)
508 module _90_modfloor (A, B, Y);
509 parameter A_SIGNED = 0;
510 parameter B_SIGNED = 0;
511 parameter A_WIDTH = 1;
512 parameter B_WIDTH = 1;
513 parameter Y_WIDTH = 1;
516 input [A_WIDTH-1:0] A;
518 input [B_WIDTH-1:0] B;
520 output [Y_WIDTH-1:0] Y;
536 // --------------------------------------------------------
538 // --------------------------------------------------------
540 (* techmap_celltype = "$pow" *)
541 module _90_pow (A, B, Y);
542 parameter A_SIGNED = 0;
543 parameter B_SIGNED = 0;
544 parameter A_WIDTH = 1;
545 parameter B_WIDTH = 1;
546 parameter Y_WIDTH = 1;
549 input [A_WIDTH-1:0] A;
551 input [B_WIDTH-1:0] B;
553 output [Y_WIDTH-1:0] Y;
555 wire _TECHMAP_FAIL_ = 1;
559 // --------------------------------------------------------
560 // Parallel Multiplexers
561 // --------------------------------------------------------
563 (* techmap_celltype = "$pmux" *)
564 module _90_pmux (A, B, S, Y);
566 parameter S_WIDTH = 1;
571 input [WIDTH*S_WIDTH-1:0] B;
573 input [S_WIDTH-1:0] S;
575 output [WIDTH-1:0] Y;
578 wire [WIDTH-1:0] Y_B;
583 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
584 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
585 assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
587 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
589 wire [S_WIDTH-1:0] B_AND_BITS;
590 for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
591 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
592 end:B_AND_BITS_COLLECT
593 assign Y_B[i] = |B_AND_BITS;
597 assign Y = |S ? Y_B : A;
600 // --------------------------------------------------------
602 // --------------------------------------------------------
604 (* techmap_celltype = "$demux" *)
605 module _90_demux (A, S, Y);
607 parameter S_WIDTH = 1;
612 input [S_WIDTH-1:0] S;
614 output [(WIDTH << S_WIDTH)-1:0] Y;
617 if (S_WIDTH == 0) begin
619 end else if (S_WIDTH == 1) begin
620 assign Y[0+:WIDTH] = S ? 0 : A;
621 assign Y[WIDTH+:WIDTH] = S ? A : 0;
623 localparam SPLIT = S_WIDTH / 2;
624 wire [(1 << (S_WIDTH-SPLIT))-1:0] YH;
625 wire [(1 << SPLIT)-1:0] YL;
626 $demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));
627 $demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));
629 for (i = 0; i < (1 << S_WIDTH); i = i + 1) begin
630 localparam [S_WIDTH-1:0] IDX = i;
631 assign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;
638 // --------------------------------------------------------
640 // --------------------------------------------------------
643 (* techmap_simplemap *)
644 (* techmap_celltype = "$lut $sop" *)