projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Using "via_celltype" in $mul carry-save-acc implementation
[yosys.git] / techlibs / common / techmap.v
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * The internal logic cell technology mapper.
21 *
22 * This verilog library contains the mapping of internal cells (e.g. $not with
23 * variable bit width) to the internal logic cells (such as the single bit $_NOT_
24 * gate). Usually this logic network is then mapped to the actual technology
25 * using e.g. the "abc" pass.
26 *
27 * Note that this library does not map $mem cells. They must be mapped to logic
28 * and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
29 * which is of course highly recommended for larger memories.)
30 *
31 */
32
33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
35
36
37 // --------------------------------------------------------
38 // Use simplemap for trivial cell types
39 // --------------------------------------------------------
40
41 (* techmap_simplemap *)
42 (* techmap_celltype = "$pos $bu0" *)
43 module simplemap_buffers;
44 endmodule
45
46 (* techmap_simplemap *)
47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
48 module simplemap_bool_ops;
49 endmodule
50
51 (* techmap_simplemap *)
52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
53 module simplemap_reduce_ops;
54 endmodule
55
56 (* techmap_simplemap *)
57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
58 module simplemap_logic_ops;
59 endmodule
60
61 (* techmap_simplemap *)
62 (* techmap_celltype = "$slice $concat $mux" *)
63 module simplemap_various;
64 endmodule
65
66 (* techmap_simplemap *)
67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
68 module simplemap_registers;
69 endmodule
70
71
72 // --------------------------------------------------------
73 // Trivial substitutions
74 // --------------------------------------------------------
75
76 module \$neg (A, Y);
77 parameter A_SIGNED = 0;
78 parameter A_WIDTH = 1;
79 parameter Y_WIDTH = 1;
80
81 input [A_WIDTH-1:0] A;
82 output [Y_WIDTH-1:0] Y;
83
84 \$sub #(
85 .A_SIGNED(A_SIGNED),
86 .B_SIGNED(A_SIGNED),
87 .A_WIDTH(1),
88 .B_WIDTH(A_WIDTH),
89 .Y_WIDTH(Y_WIDTH)
90 ) _TECHMAP_REPLACE_ (
91 .A(1'b0),
92 .B(A),
93 .Y(Y)
94 );
95 endmodule
96
97 module \$ge (A, B, Y);
98 parameter A_SIGNED = 0;
99 parameter B_SIGNED = 0;
100 parameter A_WIDTH = 1;
101 parameter B_WIDTH = 1;
102 parameter Y_WIDTH = 1;
103
104 input [A_WIDTH-1:0] A;
105 input [B_WIDTH-1:0] B;
106 output [Y_WIDTH-1:0] Y;
107
108 \$le #(
109 .A_SIGNED(B_SIGNED),
110 .B_SIGNED(A_SIGNED),
111 .A_WIDTH(B_WIDTH),
112 .B_WIDTH(A_WIDTH),
113 .Y_WIDTH(Y_WIDTH)
114 ) _TECHMAP_REPLACE_ (
115 .A(B),
116 .B(A),
117 .Y(Y)
118 );
119 endmodule
120
121 module \$gt (A, B, Y);
122 parameter A_SIGNED = 0;
123 parameter B_SIGNED = 0;
124 parameter A_WIDTH = 1;
125 parameter B_WIDTH = 1;
126 parameter Y_WIDTH = 1;
127
128 input [A_WIDTH-1:0] A;
129 input [B_WIDTH-1:0] B;
130 output [Y_WIDTH-1:0] Y;
131
132 \$lt #(
133 .A_SIGNED(B_SIGNED),
134 .B_SIGNED(A_SIGNED),
135 .A_WIDTH(B_WIDTH),
136 .B_WIDTH(A_WIDTH),
137 .Y_WIDTH(Y_WIDTH)
138 ) _TECHMAP_REPLACE_ (
139 .A(B),
140 .B(A),
141 .Y(Y)
142 );
143 endmodule
144
145
146 // --------------------------------------------------------
147 // Shift operators
148 // --------------------------------------------------------
149
150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
152 parameter A_SIGNED = 0;
153 parameter B_SIGNED = 0;
154 parameter A_WIDTH = 1;
155 parameter B_WIDTH = 1;
156 parameter Y_WIDTH = 1;
157
158 parameter _TECHMAP_CELLTYPE_ = "";
159 localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
160 localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
161
162 input [A_WIDTH-1:0] A;
163 input [B_WIDTH-1:0] B;
164 output [Y_WIDTH-1:0] Y;
165
166 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
167 localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
168
169 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
170 wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
171
172 integer i;
173 reg [WIDTH-1:0] buffer;
174 reg overflow;
175
176 always @* begin
177 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
178 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
179
180 for (i = 0; i < BB_WIDTH; i = i+1)
181 if (B[i]) begin
182 if (shift_left)
183 buffer = {buffer, (2**i)'b0};
184 else if (2**i < WIDTH)
185 buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
186 else
187 buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
188 end
189 end
190
191 assign Y = buffer;
192 endmodule
193
194 (* techmap_celltype = "$shift $shiftx" *)
195 module shift_shiftx (A, B, Y);
196 parameter A_SIGNED = 0;
197 parameter B_SIGNED = 0;
198 parameter A_WIDTH = 1;
199 parameter B_WIDTH = 1;
200 parameter Y_WIDTH = 1;
201
202 input [A_WIDTH-1:0] A;
203 input [B_WIDTH-1:0] B;
204 output [Y_WIDTH-1:0] Y;
205
206 localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
207 localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
208
209 parameter _TECHMAP_CELLTYPE_ = "";
210 localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
211
212 wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
213 wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
214
215 integer i;
216 reg [WIDTH-1:0] buffer;
217 reg overflow;
218
219 always @* begin
220 overflow = 0;
221 buffer = {WIDTH{extbit}};
222 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
223
224 if (B_WIDTH > BB_WIDTH) begin
225 if (B_SIGNED) begin
226 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
227 if (B[i] != B[BB_WIDTH-1])
228 overflow = 1;
229 end else
230 overflow = |B[B_WIDTH-1:BB_WIDTH];
231 if (overflow)
232 buffer = {WIDTH{extbit}};
233 end
234
235 for (i = BB_WIDTH-1; i >= 0; i = i-1)
236 if (B[i]) begin
237 if (B_SIGNED && i == BB_WIDTH-1)
238 buffer = {buffer, {2**i{extbit}}};
239 else if (2**i < WIDTH)
240 buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
241 else
242 buffer = {WIDTH{extbit}};
243 end
244 end
245
246 assign Y = buffer;
247 endmodule
248
249
250 // --------------------------------------------------------
251 // ALU Infrastructure
252 // --------------------------------------------------------
253
254 module \$__alu_ripple (A, B, CI, X, Y, CO, CS);
255 parameter WIDTH = 1;
256
257 input [WIDTH-1:0] A, B;
258 output [WIDTH-1:0] X, Y;
259
260 input CI;
261 output CO, CS;
262
263 wire [WIDTH:0] carry;
264 assign carry[0] = CI;
265 assign CO = carry[WIDTH];
266 assign CS = carry[WIDTH-1];
267
268 genvar i;
269 generate
270 for (i = 0; i < WIDTH; i = i+1)
271 begin:V
272 // {x, y} = a + b + c
273 wire a, b, c, x, y;
274 wire t1, t2, t3;
275
276 \$_AND_ gate1 ( .A(a), .B(b), .Y(t1) );
277 \$_XOR_ gate2 ( .A(a), .B(b), .Y(t2) );
278 \$_AND_ gate3 ( .A(t2), .B(c), .Y(t3) );
279 \$_XOR_ gate4 ( .A(t2), .B(c), .Y(y) );
280 \$_OR_ gate5 ( .A(t1), .B(t3), .Y(x) );
281
282 assign a = A[i], b = B[i], c = carry[i];
283 assign carry[i+1] = x, X[i] = t2, Y[i] = y;
284 end
285 endgenerate
286 endmodule
287
288 module \$__lcu (P, G, CI, CO);
289 parameter WIDTH = 2;
290
291 input [WIDTH-1:0] P, G;
292 input CI;
293
294 output reg [WIDTH:0] CO;
295
296 integer i, j;
297 reg [WIDTH-1:0] p, g;
298
299 wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
300
301 always @* begin
302 p = P;
303 g = G;
304
305 // in almost all cases CI will be constant zero
306 g[0] = g[0] | (p[0] & CI);
307
308 // [[CITE]] Brent Kung Adder
309 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
310 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
311
312 // Main tree
313 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
314 for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
315 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
316 p[j] = p[j] & p[j - 2**(i-1)];
317 end
318 end
319
320 // Inverse tree
321 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
322 for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
323 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
324 p[j] = p[j] & p[j - 2**(i-1)];
325 end
326 end
327 end
328
329 assign CO = {g, CI};
330 endmodule
331
332 module \$__alu_lookahead (A, B, CI, X, Y, CO, CS);
333 parameter WIDTH = 1;
334
335 input [WIDTH-1:0] A, B;
336 output [WIDTH-1:0] X, Y;
337
338 input CI;
339 output CO, CS;
340
341 wire [WIDTH-1:0] P, G;
342 wire [WIDTH:0] C;
343
344 assign CO = C[WIDTH];
345 assign CS = C[WIDTH-1];
346
347 genvar i;
348 generate
349 for (i = 0; i < WIDTH; i = i+1)
350 begin:V
351 wire a, b, c, p, g, y;
352
353 \$_AND_ gate1 ( .A(a), .B(b), .Y(g) );
354 \$_XOR_ gate2 ( .A(a), .B(b), .Y(p) );
355 \$_XOR_ gate3 ( .A(p), .B(c), .Y(y) );
356
357 assign a = A[i], b = B[i], c = C[i];
358 assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
359 end
360 endgenerate
361
362 \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(C));
363 endmodule
364
365 module \$__alu (A, B, CI, BI, X, Y, CO, CS);
366 parameter A_SIGNED = 0;
367 parameter B_SIGNED = 0;
368 parameter A_WIDTH = 1;
369 parameter B_WIDTH = 1;
370 parameter Y_WIDTH = 1;
371
372 input [A_WIDTH-1:0] A;
373 input [B_WIDTH-1:0] B;
374 output [Y_WIDTH-1:0] X, Y;
375
376 // carry in, sub, carry out, carry sign
377 input CI, BI;
378 output CO, CS;
379
380 wire [Y_WIDTH-1:0] A_buf, B_buf;
381 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
382 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
383
384 `ifdef ALU_RIPPLE
385 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
386 `else
387 if (Y_WIDTH <= 4) begin
388 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
389 end else begin
390 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO), .CS(CS));
391 end
392 `endif
393 endmodule
394
395
396 // --------------------------------------------------------
397 // ALU Cell Types: Compare, Add, Subtract
398 // --------------------------------------------------------
399
400 `define ALU_COMMONS(_width, _ci, _bi) """
401 parameter A_SIGNED = 0;
402 parameter B_SIGNED = 0;
403 parameter A_WIDTH = 1;
404 parameter B_WIDTH = 1;
405 parameter Y_WIDTH = 1;
406
407 localparam WIDTH = _width;
408
409 input [A_WIDTH-1:0] A;
410 input [B_WIDTH-1:0] B;
411 output [Y_WIDTH-1:0] Y;
412
413 wire alu_co, alu_cs;
414 wire [WIDTH-1:0] alu_x, alu_y;
415
416 \$__alu #(
417 .A_SIGNED(A_SIGNED),
418 .B_SIGNED(B_SIGNED),
419 .A_WIDTH(A_WIDTH),
420 .B_WIDTH(B_WIDTH),
421 .Y_WIDTH(WIDTH)
422 ) alu (
423 .A(A),
424 .B(B),
425 .CI(_ci),
426 .BI(_bi),
427 .X(alu_x),
428 .Y(alu_y),
429 .CO(alu_co),
430 .CS(alu_cs)
431 );
432
433 wire cf, of, zf, sf;
434 assign cf = !alu_co;
435 assign of = alu_co ^ alu_cs;
436 assign sf = alu_y[WIDTH-1];
437 """
438
439 module \$lt (A, B, Y);
440 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
441 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
442 assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
443 endmodule
444
445 module \$le (A, B, Y);
446 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
447 `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
448 assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
449 endmodule
450
451 module \$add (A, B, Y);
452 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
453 `ALU_COMMONS(Y_WIDTH, 0, 0)
454 assign Y = alu_y;
455 endmodule
456
457 module \$sub (A, B, Y);
458 wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
459 `ALU_COMMONS(Y_WIDTH, 1, 1)
460 assign Y = alu_y;
461 endmodule
462
463
464 // --------------------------------------------------------
465 // Multiply
466 // --------------------------------------------------------
467
468 module \$__acc_set (acc_new, value);
469 parameter WIDTH = 1;
470 output reg [2*WIDTH-1:0] acc_new;
471 input [WIDTH-1:0] value;
472
473 wire [1023:0] _TECHMAP_DO_ = "proc;;;";
474
475 integer k;
476 always @* begin
477 for (k = 0; k < WIDTH; k = k+1) begin
478 acc_new[2*k +: 2] = value[k];
479 end
480 end
481 endmodule
482
483 module \$__acc_add (acc_new, acc_old, value);
484 parameter WIDTH = 1;
485 output reg [2*WIDTH-1:0] acc_new;
486 input [2*WIDTH-1:0] acc_old;
487 input [WIDTH-1:0] value;
488
489 wire [1023:0] _TECHMAP_DO_ = "proc; simplemap; opt -purge";
490
491 integer k;
492 reg a, b, c;
493
494 always @* begin
495 for (k = 0; k < WIDTH; k = k+1) begin
496 a = acc_old[2*k];
497 b = k ? acc_old[2*k-1] : 1'b0;
498 c = value[k];
499 acc_new[2*k] = (a ^ b) ^ c;
500 acc_new[2*k+1] = (a & b) | ((a ^ b) & c);
501 end
502 end
503 endmodule
504
505 module \$__acc_get (value, acc);
506 parameter WIDTH = 1;
507 output reg [WIDTH-1:0] value;
508 input [2*WIDTH-1:0] acc;
509
510 wire [1023:0] _TECHMAP_DO_ = "proc;;;";
511
512 integer k;
513
514 always @* begin
515 // at the end of the multiplier chain the carry-save accumulator
516 // should also have propagated all carries. thus we just need to
517 // copy the even bits from the carry accumulator to the output.
518 for (k = 0; k < WIDTH; k = k+1) begin
519 value[k] = acc[2*k];
520 end
521 end
522 endmodule
523
524 module \$__acc_mul (A, B, Y);
525 parameter WIDTH = 1;
526 input [WIDTH-1:0] A, B;
527 output [WIDTH-1:0] Y;
528
529 wire [1023:0] _TECHMAP_DO_ = "proc;;";
530
531 integer i;
532 reg [WIDTH-1:0] x;
533 reg [2*WIDTH-1:0] y;
534
535 (* via_celltype = "\\$__acc_set acc_new" *)
536 (* via_celltype_defparam_WIDTH = WIDTH *)
537 function [2*WIDTH-1:0] acc_set;
538 input [WIDTH-1:0] value;
539 endfunction
540
541 (* via_celltype = "\\$__acc_add acc_new" *)
542 (* via_celltype_defparam_WIDTH = WIDTH *)
543 function [2*WIDTH-1:0] acc_add;
544 input [2*WIDTH-1:0] acc_old;
545 input [WIDTH-1:0] value;
546 endfunction
547
548 (* via_celltype = "\\$__acc_get value" *)
549 (* via_celltype_defparam_WIDTH = WIDTH *)
550 function [WIDTH-1:0] acc_get;
551 input [2*WIDTH-1:0] acc;
552 endfunction
553
554 always @* begin
555 x = B;
556 y = acc_set(A[0] ? x : 1'b0);
557 for (i = 1; i < WIDTH; i = i+1) begin
558 x = {x[WIDTH-2:0], 1'b0};
559 y = acc_add(y, A[i] ? x : 1'b0);
560 end
561 end
562
563 assign Y = acc_get(y);
564 endmodule
565
566 module \$mul (A, B, Y);
567 parameter A_SIGNED = 0;
568 parameter B_SIGNED = 0;
569 parameter A_WIDTH = 1;
570 parameter B_WIDTH = 1;
571 parameter Y_WIDTH = 1;
572
573 input [A_WIDTH-1:0] A;
574 input [B_WIDTH-1:0] B;
575 output [Y_WIDTH-1:0] Y;
576
577 wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
578
579 wire [Y_WIDTH-1:0] A_buf, B_buf;
580 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
581 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
582
583 \$__acc_mul #(
584 .WIDTH(Y_WIDTH)
585 ) _TECHMAP_REPLACE_ (
586 .A(A_buf),
587 .B(B_buf),
588 .Y(Y)
589 );
590 endmodule
591
592
593 // --------------------------------------------------------
594 // Divide and Modulo
595 // --------------------------------------------------------
596
597 module \$__div_mod_u (A, B, Y, R);
598 parameter WIDTH = 1;
599
600 input [WIDTH-1:0] A, B;
601 output [WIDTH-1:0] Y, R;
602
603 wire [WIDTH*WIDTH-1:0] chaindata;
604 assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
605
606 genvar i;
607 generate begin
608 for (i = 0; i < WIDTH; i=i+1) begin:stage
609 wire [WIDTH-1:0] stage_in;
610
611 if (i == 0) begin:cp
612 assign stage_in = A;
613 end else begin:cp
614 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
615 end
616
617 assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
618 assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
619 end
620 end endgenerate
621 endmodule
622
623 module \$__div_mod (A, B, Y, R);
624 parameter A_SIGNED = 0;
625 parameter B_SIGNED = 0;
626 parameter A_WIDTH = 1;
627 parameter B_WIDTH = 1;
628 parameter Y_WIDTH = 1;
629
630 localparam WIDTH =
631 A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
632 B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
633
634 input [A_WIDTH-1:0] A;
635 input [B_WIDTH-1:0] B;
636 output [Y_WIDTH-1:0] Y, R;
637
638 wire [WIDTH-1:0] A_buf, B_buf;
639 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
640 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
641
642 wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
643 assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
644 assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
645
646 \$__div_mod_u #(
647 .WIDTH(WIDTH)
648 ) div_mod_u (
649 .A(A_buf_u),
650 .B(B_buf_u),
651 .Y(Y_u),
652 .R(R_u)
653 );
654
655 assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
656 assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
657 endmodule
658
659 module \$div (A, B, Y);
660 parameter A_SIGNED = 0;
661 parameter B_SIGNED = 0;
662 parameter A_WIDTH = 1;
663 parameter B_WIDTH = 1;
664 parameter Y_WIDTH = 1;
665
666 input [A_WIDTH-1:0] A;
667 input [B_WIDTH-1:0] B;
668 output [Y_WIDTH-1:0] Y;
669
670 \$__div_mod #(
671 .A_SIGNED(A_SIGNED),
672 .B_SIGNED(B_SIGNED),
673 .A_WIDTH(A_WIDTH),
674 .B_WIDTH(B_WIDTH),
675 .Y_WIDTH(Y_WIDTH)
676 ) div_mod (
677 .A(A),
678 .B(B),
679 .Y(Y)
680 );
681 endmodule
682
683 module \$mod (A, B, Y);
684 parameter A_SIGNED = 0;
685 parameter B_SIGNED = 0;
686 parameter A_WIDTH = 1;
687 parameter B_WIDTH = 1;
688 parameter Y_WIDTH = 1;
689
690 input [A_WIDTH-1:0] A;
691 input [B_WIDTH-1:0] B;
692 output [Y_WIDTH-1:0] Y;
693
694 \$__div_mod #(
695 .A_SIGNED(A_SIGNED),
696 .B_SIGNED(B_SIGNED),
697 .A_WIDTH(A_WIDTH),
698 .B_WIDTH(B_WIDTH),
699 .Y_WIDTH(Y_WIDTH)
700 ) div_mod (
701 .A(A),
702 .B(B),
703 .R(Y)
704 );
705 endmodule
706
707
708 // --------------------------------------------------------
709 // Power
710 // --------------------------------------------------------
711
712 module \$pow (A, B, Y);
713 parameter A_SIGNED = 0;
714 parameter B_SIGNED = 0;
715 parameter A_WIDTH = 1;
716 parameter B_WIDTH = 1;
717 parameter Y_WIDTH = 1;
718
719 input [A_WIDTH-1:0] A;
720 input [B_WIDTH-1:0] B;
721 output [Y_WIDTH-1:0] Y;
722
723 wire _TECHMAP_FAIL_ = 1;
724 endmodule
725
726
727 // --------------------------------------------------------
728 // Equal and Not-Equal
729 // --------------------------------------------------------
730
731 module \$eq (A, B, Y);
732 parameter A_SIGNED = 0;
733 parameter B_SIGNED = 0;
734 parameter A_WIDTH = 1;
735 parameter B_WIDTH = 1;
736 parameter Y_WIDTH = 1;
737
738 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
739
740 input [A_WIDTH-1:0] A;
741 input [B_WIDTH-1:0] B;
742 output [Y_WIDTH-1:0] Y;
743
744 wire carry, carry_sign;
745 wire [WIDTH-1:0] A_buf, B_buf;
746 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
747 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
748
749 assign Y = ~|(A_buf ^ B_buf);
750 endmodule
751
752 module \$ne (A, B, Y);
753 parameter A_SIGNED = 0;
754 parameter B_SIGNED = 0;
755 parameter A_WIDTH = 1;
756 parameter B_WIDTH = 1;
757 parameter Y_WIDTH = 1;
758
759 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
760
761 input [A_WIDTH-1:0] A;
762 input [B_WIDTH-1:0] B;
763 output [Y_WIDTH-1:0] Y;
764
765 wire carry, carry_sign;
766 wire [WIDTH-1:0] A_buf, B_buf;
767 \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
768 \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
769
770 assign Y = |(A_buf ^ B_buf);
771 endmodule
772
773 module \$eqx (A, B, Y);
774 parameter A_SIGNED = 0;
775 parameter B_SIGNED = 0;
776 parameter A_WIDTH = 1;
777 parameter B_WIDTH = 1;
778 parameter Y_WIDTH = 1;
779
780 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
781
782 input [A_WIDTH-1:0] A;
783 input [B_WIDTH-1:0] B;
784 output [Y_WIDTH-1:0] Y;
785
786 wire carry, carry_sign;
787 wire [WIDTH-1:0] A_buf, B_buf;
788 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
789 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
790
791 assign Y = ~|(A_buf ^ B_buf);
792 endmodule
793
794 module \$nex (A, B, Y);
795 parameter A_SIGNED = 0;
796 parameter B_SIGNED = 0;
797 parameter A_WIDTH = 1;
798 parameter B_WIDTH = 1;
799 parameter Y_WIDTH = 1;
800
801 localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
802
803 input [A_WIDTH-1:0] A;
804 input [B_WIDTH-1:0] B;
805 output [Y_WIDTH-1:0] Y;
806
807 wire carry, carry_sign;
808 wire [WIDTH-1:0] A_buf, B_buf;
809 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
810 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
811
812 assign Y = |(A_buf ^ B_buf);
813 endmodule
814
815
816 // --------------------------------------------------------
817 // Parallel Multiplexers
818 // --------------------------------------------------------
819
820 module \$pmux (A, B, S, Y);
821 parameter WIDTH = 1;
822 parameter S_WIDTH = 1;
823
824 input [WIDTH-1:0] A;
825 input [WIDTH*S_WIDTH-1:0] B;
826 input [S_WIDTH-1:0] S;
827 output [WIDTH-1:0] Y;
828
829 wire [WIDTH-1:0] Y_B;
830
831 genvar i, j;
832 generate
833 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
834 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
835 assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
836 end:B_AND
837 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
838 wire [S_WIDTH-1:0] B_AND_BITS;
839 for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
840 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
841 end:B_AND_BITS_COLLECT
842 assign Y_B[i] = |B_AND_BITS;
843 end:B_OR
844 endgenerate
845
846 assign Y = |S ? Y_B : A;
847 endmodule
848