techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_INV_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$pos $bu0" *)
  43 module simplemap_buffers;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  48 module simplemap_bool_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  53 module simplemap_reduce_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  58 module simplemap_logic_ops;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$slice $concat $mux" *)
  63 module simplemap_various;
  64 endmodule
  65
  66 (* techmap_simplemap *)
  67 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  68 module simplemap_registers;
  69 endmodule
  70
  71
  72 // --------------------------------------------------------
  73 // Trivial substitutions
  74 // --------------------------------------------------------
  75
  76 module \$neg (A, Y);
  77         parameter A_SIGNED = 0;
  78         parameter A_WIDTH = 1;
  79         parameter Y_WIDTH = 1;
  80
  81         input [A_WIDTH-1:0] A;
  82         output [Y_WIDTH-1:0] Y;
  83
  84         \$sub #(
  85                 .A_SIGNED(A_SIGNED),
  86                 .B_SIGNED(A_SIGNED),
  87                 .A_WIDTH(1),
  88                 .B_WIDTH(A_WIDTH),
  89                 .Y_WIDTH(Y_WIDTH)
  90         ) _TECHMAP_REPLACE_ (
  91                 .A(1'b0),
  92                 .B(A),
  93                 .Y(Y)
  94         );
  95 endmodule
  96
  97 module \$ge (A, B, Y);
  98         parameter A_SIGNED = 0;
  99         parameter B_SIGNED = 0;
 100         parameter A_WIDTH = 1;
 101         parameter B_WIDTH = 1;
 102         parameter Y_WIDTH = 1;
 103
 104         input [A_WIDTH-1:0] A;
 105         input [B_WIDTH-1:0] B;
 106         output [Y_WIDTH-1:0] Y;
 107
 108         \$le #(
 109                 .A_SIGNED(B_SIGNED),
 110                 .B_SIGNED(A_SIGNED),
 111                 .A_WIDTH(B_WIDTH),
 112                 .B_WIDTH(A_WIDTH),
 113                 .Y_WIDTH(Y_WIDTH)
 114         ) _TECHMAP_REPLACE_ (
 115                 .A(B),
 116                 .B(A),
 117                 .Y(Y)
 118         );
 119 endmodule
 120
 121 module \$gt (A, B, Y);
 122         parameter A_SIGNED = 0;
 123         parameter B_SIGNED = 0;
 124         parameter A_WIDTH = 1;
 125         parameter B_WIDTH = 1;
 126         parameter Y_WIDTH = 1;
 127
 128         input [A_WIDTH-1:0] A;
 129         input [B_WIDTH-1:0] B;
 130         output [Y_WIDTH-1:0] Y;
 131
 132         \$lt #(
 133                 .A_SIGNED(B_SIGNED),
 134                 .B_SIGNED(A_SIGNED),
 135                 .A_WIDTH(B_WIDTH),
 136                 .B_WIDTH(A_WIDTH),
 137                 .Y_WIDTH(Y_WIDTH)
 138         ) _TECHMAP_REPLACE_ (
 139                 .A(B),
 140                 .B(A),
 141                 .Y(Y)
 142         );
 143 endmodule
 144
 145
 146 // --------------------------------------------------------
 147 // Shift operators
 148 // --------------------------------------------------------
 149
 150 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 151 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 152         parameter A_SIGNED = 0;
 153         parameter B_SIGNED = 0;
 154         parameter A_WIDTH = 1;
 155         parameter B_WIDTH = 1;
 156         parameter Y_WIDTH = 1;
 157
 158         parameter _TECHMAP_CELLTYPE_ = "";
 159         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 160         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 161
 162         input [A_WIDTH-1:0] A;
 163         input [B_WIDTH-1:0] B;
 164         output [Y_WIDTH-1:0] Y;
 165
 166         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 167         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 168
 169         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 170         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 171
 172         integer i;
 173         reg [WIDTH-1:0] buffer;
 174         reg overflow;
 175
 176         always @* begin
 177                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 178                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 179
 180                 for (i = 0; i < BB_WIDTH; i = i+1)
 181                         if (B[i]) begin
 182                                 if (shift_left)
 183                                         buffer = {buffer, (2**i)'b0};
 184                                 else if (2**i < WIDTH)
 185                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 186                                 else
 187                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 188                         end
 189         end
 190
 191         assign Y = buffer;
 192 endmodule
 193
 194 (* techmap_celltype = "$shift $shiftx" *)
 195 module shift_shiftx (A, B, Y);
 196         parameter A_SIGNED = 0;
 197         parameter B_SIGNED = 0;
 198         parameter A_WIDTH = 1;
 199         parameter B_WIDTH = 1;
 200         parameter Y_WIDTH = 1;
 201
 202         input [A_WIDTH-1:0] A;
 203         input [B_WIDTH-1:0] B;
 204         output [Y_WIDTH-1:0] Y;
 205
 206         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 207         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 208
 209         parameter _TECHMAP_CELLTYPE_ = "";
 210         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 211
 212         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 213         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 214
 215         integer i;
 216         reg [WIDTH-1:0] buffer;
 217         reg overflow;
 218
 219         always @* begin
 220                 overflow = 0;
 221                 buffer = {WIDTH{extbit}};
 222                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 223
 224                 if (B_WIDTH > BB_WIDTH) begin
 225                         if (B_SIGNED) begin
 226                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 227                                         if (B[i] != B[BB_WIDTH-1])
 228                                                 overflow = 1;
 229                         end else
 230                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 231                         if (overflow)
 232                                 buffer = {WIDTH{extbit}};
 233                 end
 234
 235                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 236                         if (B[i]) begin
 237                                 if (B_SIGNED && i == BB_WIDTH-1)
 238                                         buffer = {buffer, {2**i{extbit}}};
 239                                 else if (2**i < WIDTH)
 240                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 241                                 else
 242                                         buffer = {WIDTH{extbit}};
 243                         end
 244         end
 245
 246         assign Y = buffer;
 247 endmodule
 248
 249
 250 // --------------------------------------------------------
 251 // ALU Infrastructure
 252 // --------------------------------------------------------
 253
 254 module \$__fulladd (A, B, C, X, Y);
 255         // {X, Y} = A + B + C
 256         input A, B, C;
 257         output X, Y;
 258
 259         // {t1, t2} = A + B
 260         wire t1, t2, t3;
 261
 262         \$_AND_ gate1 ( .A(A),  .B(B),  .Y(t1) );
 263         \$_XOR_ gate2 ( .A(A),  .B(B),  .Y(t2) );
 264         \$_AND_ gate3 ( .A(t2), .B(C),  .Y(t3) );
 265         \$_XOR_ gate4 ( .A(t2), .B(C),  .Y(Y)  );
 266         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(X)  );
 267 endmodule
 268
 269 module \$__alu (A, B, CI, S, Y, CO, CS);
 270         parameter A_SIGNED = 0;
 271         parameter B_SIGNED = 0;
 272         parameter A_WIDTH = 1;
 273         parameter B_WIDTH = 1;
 274         parameter Y_WIDTH = 1;
 275
 276         input [A_WIDTH-1:0] A;
 277         input [B_WIDTH-1:0] B;
 278         output [Y_WIDTH-1:0] Y;
 279
 280         // carry in, sub, carry out, carry sign
 281         input CI, S;
 282         output CO, CS;
 283
 284         wire [Y_WIDTH-1:0] A_buf, B_buf;
 285         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 286         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 287
 288         wire [Y_WIDTH:0] carry;
 289         assign carry[0] = CI;
 290         assign CO = carry[Y_WIDTH];
 291         assign CS = carry[Y_WIDTH-1];
 292
 293         genvar i;
 294         generate
 295                 for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
 296                         \$__fulladd adder (
 297                                 .A(A_buf[i]),
 298                                 .B(S ? !B_buf[i] : B_buf[i]),
 299                                 .C(carry[i]),
 300                                 .X(carry[i+1]),
 301                                 .Y(Y[i])
 302                         );
 303                 end
 304         endgenerate
 305 endmodule
 306
 307 `define ALU_COMMONS(_width, _ci, _s) """
 308         parameter A_SIGNED = 0;
 309         parameter B_SIGNED = 0;
 310         parameter A_WIDTH = 1;
 311         parameter B_WIDTH = 1;
 312         parameter Y_WIDTH = 1;
 313
 314         localparam WIDTH = _width;
 315
 316         input [A_WIDTH-1:0] A;
 317         input [B_WIDTH-1:0] B;
 318         output [Y_WIDTH-1:0] Y;
 319
 320         wire alu_co, alu_cs;
 321         wire [WIDTH-1:0] alu_y;
 322
 323         \$__alu #(
 324                 .A_SIGNED(A_SIGNED),
 325                 .B_SIGNED(B_SIGNED),
 326                 .A_WIDTH(A_WIDTH),
 327                 .B_WIDTH(B_WIDTH),
 328                 .Y_WIDTH(WIDTH)
 329         ) alu (
 330                 .A(A),
 331                 .B(B),
 332                 .CI(_ci),
 333                 .S(_s),
 334                 .Y(alu_y),
 335                 .CO(alu_co),
 336                 .CS(alu_cs)
 337         );
 338
 339         wire cf, of, zf, sf;
 340         assign cf = !alu_co;
 341         assign of = alu_co ^ alu_cs;
 342         assign zf = ~|alu_y;
 343         assign sf = alu_y[WIDTH-1];
 344 """
 345
 346
 347 // --------------------------------------------------------
 348 // Compare cells
 349 // --------------------------------------------------------
 350
 351 module \$lt (A, B, Y);
 352         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 353         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 354         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 355 endmodule
 356
 357 module \$le (A, B, Y);
 358         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 359         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1, 1)
 360         assign Y = zf || (A_SIGNED && B_SIGNED ? of != sf : cf);
 361 endmodule
 362
 363
 364 // --------------------------------------------------------
 365 // Add and Subtract
 366 // --------------------------------------------------------
 367
 368 module \$add (A, B, Y);
 369         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 370         `ALU_COMMONS(Y_WIDTH, 0, 0)
 371         assign Y = alu_y;
 372 endmodule
 373
 374 module \$sub (A, B, Y);
 375         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt_const -mux_undef -mux_bool -fine;;;";
 376         `ALU_COMMONS(Y_WIDTH, 1, 1)
 377         assign Y = alu_y;
 378 endmodule
 379
 380
 381 // --------------------------------------------------------
 382 // Multiply
 383 // --------------------------------------------------------
 384
 385 module \$__arraymul (A, B, Y);
 386         parameter WIDTH = 8;
 387         input [WIDTH-1:0] A, B;
 388         output [WIDTH-1:0] Y;
 389
 390         wire [WIDTH*WIDTH-1:0] partials;
 391
 392         genvar i;
 393         assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
 394         generate for (i = 1; i < WIDTH; i = i+1) begin:gen
 395                 assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
 396         end endgenerate
 397
 398         assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
 399 endmodule
 400
 401 module \$mul (A, B, Y);
 402         parameter A_SIGNED = 0;
 403         parameter B_SIGNED = 0;
 404         parameter A_WIDTH = 1;
 405         parameter B_WIDTH = 1;
 406         parameter Y_WIDTH = 1;
 407
 408         input [A_WIDTH-1:0] A;
 409         input [B_WIDTH-1:0] B;
 410         output [Y_WIDTH-1:0] Y;
 411
 412         wire [Y_WIDTH-1:0] A_buf, B_buf;
 413         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 414         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 415
 416         \$__arraymul #(
 417                 .WIDTH(Y_WIDTH)
 418         ) arraymul (
 419                 .A(A_buf),
 420                 .B(B_buf),
 421                 .Y(Y)
 422         );
 423 endmodule
 424
 425
 426 // --------------------------------------------------------
 427 // Divide and Modulo
 428 // --------------------------------------------------------
 429
 430 module \$__div_mod_u (A, B, Y, R);
 431         parameter WIDTH = 1;
 432
 433         input [WIDTH-1:0] A, B;
 434         output [WIDTH-1:0] Y, R;
 435
 436         wire [WIDTH*WIDTH-1:0] chaindata;
 437         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 438
 439         genvar i;
 440         generate begin
 441                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 442                         wire [WIDTH-1:0] stage_in;
 443
 444                         if (i == 0) begin:cp
 445                                 assign stage_in = A;
 446                         end else begin:cp
 447                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 448                         end
 449
 450                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 451                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 452                 end
 453         end endgenerate
 454 endmodule
 455
 456 module \$__div_mod (A, B, Y, R);
 457         parameter A_SIGNED = 0;
 458         parameter B_SIGNED = 0;
 459         parameter A_WIDTH = 1;
 460         parameter B_WIDTH = 1;
 461         parameter Y_WIDTH = 1;
 462
 463         localparam WIDTH =
 464                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 465                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 466
 467         input [A_WIDTH-1:0] A;
 468         input [B_WIDTH-1:0] B;
 469         output [Y_WIDTH-1:0] Y, R;
 470
 471         wire [WIDTH-1:0] A_buf, B_buf;
 472         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 473         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 474
 475         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 476         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 477         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 478
 479         \$__div_mod_u #(
 480                 .WIDTH(WIDTH)
 481         ) div_mod_u (
 482                 .A(A_buf_u),
 483                 .B(B_buf_u),
 484                 .Y(Y_u),
 485                 .R(R_u)
 486         );
 487
 488         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 489         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 490 endmodule
 491
 492 module \$div (A, B, Y);
 493         parameter A_SIGNED = 0;
 494         parameter B_SIGNED = 0;
 495         parameter A_WIDTH = 1;
 496         parameter B_WIDTH = 1;
 497         parameter Y_WIDTH = 1;
 498
 499         input [A_WIDTH-1:0] A;
 500         input [B_WIDTH-1:0] B;
 501         output [Y_WIDTH-1:0] Y;
 502
 503         \$__div_mod #(
 504                 .A_SIGNED(A_SIGNED),
 505                 .B_SIGNED(B_SIGNED),
 506                 .A_WIDTH(A_WIDTH),
 507                 .B_WIDTH(B_WIDTH),
 508                 .Y_WIDTH(Y_WIDTH)
 509         ) div_mod (
 510                 .A(A),
 511                 .B(B),
 512                 .Y(Y)
 513         );
 514 endmodule
 515
 516 module \$mod (A, B, Y);
 517         parameter A_SIGNED = 0;
 518         parameter B_SIGNED = 0;
 519         parameter A_WIDTH = 1;
 520         parameter B_WIDTH = 1;
 521         parameter Y_WIDTH = 1;
 522
 523         input [A_WIDTH-1:0] A;
 524         input [B_WIDTH-1:0] B;
 525         output [Y_WIDTH-1:0] Y;
 526
 527         \$__div_mod #(
 528                 .A_SIGNED(A_SIGNED),
 529                 .B_SIGNED(B_SIGNED),
 530                 .A_WIDTH(A_WIDTH),
 531                 .B_WIDTH(B_WIDTH),
 532                 .Y_WIDTH(Y_WIDTH)
 533         ) div_mod (
 534                 .A(A),
 535                 .B(B),
 536                 .R(Y)
 537         );
 538 endmodule
 539
 540
 541 // --------------------------------------------------------
 542 // Power
 543 // --------------------------------------------------------
 544
 545 module \$pow (A, B, Y);
 546         parameter A_SIGNED = 0;
 547         parameter B_SIGNED = 0;
 548         parameter A_WIDTH = 1;
 549         parameter B_WIDTH = 1;
 550         parameter Y_WIDTH = 1;
 551
 552         input [A_WIDTH-1:0] A;
 553         input [B_WIDTH-1:0] B;
 554         output [Y_WIDTH-1:0] Y;
 555
 556         wire _TECHMAP_FAIL_ = 1;
 557 endmodule
 558
 559
 560 // --------------------------------------------------------
 561 // Equal and Not-Equal
 562 // --------------------------------------------------------
 563
 564 module \$eq (A, B, Y);
 565         parameter A_SIGNED = 0;
 566         parameter B_SIGNED = 0;
 567         parameter A_WIDTH = 1;
 568         parameter B_WIDTH = 1;
 569         parameter Y_WIDTH = 1;
 570
 571         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 572
 573         input [A_WIDTH-1:0] A;
 574         input [B_WIDTH-1:0] B;
 575         output [Y_WIDTH-1:0] Y;
 576
 577         wire carry, carry_sign;
 578         wire [WIDTH-1:0] A_buf, B_buf;
 579         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 580         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 581
 582         assign Y = ~|(A_buf ^ B_buf);
 583 endmodule
 584
 585 module \$ne (A, B, Y);
 586         parameter A_SIGNED = 0;
 587         parameter B_SIGNED = 0;
 588         parameter A_WIDTH = 1;
 589         parameter B_WIDTH = 1;
 590         parameter Y_WIDTH = 1;
 591
 592         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 593
 594         input [A_WIDTH-1:0] A;
 595         input [B_WIDTH-1:0] B;
 596         output [Y_WIDTH-1:0] Y;
 597
 598         wire carry, carry_sign;
 599         wire [WIDTH-1:0] A_buf, B_buf;
 600         \$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 601         \$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 602
 603         assign Y = |(A_buf ^ B_buf);
 604 endmodule
 605
 606 module \$eqx (A, B, Y);
 607         parameter A_SIGNED = 0;
 608         parameter B_SIGNED = 0;
 609         parameter A_WIDTH = 1;
 610         parameter B_WIDTH = 1;
 611         parameter Y_WIDTH = 1;
 612
 613         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 614
 615         input [A_WIDTH-1:0] A;
 616         input [B_WIDTH-1:0] B;
 617         output [Y_WIDTH-1:0] Y;
 618
 619         wire carry, carry_sign;
 620         wire [WIDTH-1:0] A_buf, B_buf;
 621         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 622         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 623
 624         assign Y = ~|(A_buf ^ B_buf);
 625 endmodule
 626
 627 module \$nex (A, B, Y);
 628         parameter A_SIGNED = 0;
 629         parameter B_SIGNED = 0;
 630         parameter A_WIDTH = 1;
 631         parameter B_WIDTH = 1;
 632         parameter Y_WIDTH = 1;
 633
 634         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 635
 636         input [A_WIDTH-1:0] A;
 637         input [B_WIDTH-1:0] B;
 638         output [Y_WIDTH-1:0] Y;
 639
 640         wire carry, carry_sign;
 641         wire [WIDTH-1:0] A_buf, B_buf;
 642         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 643         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 644
 645         assign Y = |(A_buf ^ B_buf);
 646 endmodule
 647
 648
 649 // --------------------------------------------------------
 650 // Parallel Multiplexers
 651 // --------------------------------------------------------
 652
 653 module \$pmux (A, B, S, Y);
 654         parameter WIDTH = 1;
 655         parameter S_WIDTH = 1;
 656
 657         input [WIDTH-1:0] A;
 658         input [WIDTH*S_WIDTH-1:0] B;
 659         input [S_WIDTH-1:0] S;
 660         output [WIDTH-1:0] Y;
 661
 662         wire [WIDTH-1:0] Y_B;
 663
 664         genvar i, j;
 665         generate
 666                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 667                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 668                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 669                 end:B_AND
 670                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 671                         wire [S_WIDTH-1:0] B_AND_BITS;
 672                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 673                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 674                         end:B_AND_BITS_COLLECT
 675                         assign Y_B[i] = |B_AND_BITS;
 676                 end:B_OR
 677         endgenerate
 678
 679         assign Y = |S ? Y_B : A;
 680 endmodule
 681
 682 module \$safe_pmux (A, B, S, Y);
 683         parameter WIDTH = 1;
 684         parameter S_WIDTH = 1;
 685
 686         input [WIDTH-1:0] A;
 687         input [WIDTH*S_WIDTH-1:0] B;
 688         input [S_WIDTH-1:0] S;
 689         output [WIDTH-1:0] Y;
 690
 691         wire [S_WIDTH-1:0] status_found_first;
 692         wire [S_WIDTH-1:0] status_found_second;
 693
 694         genvar i;
 695         generate
 696                 for (i = 0; i < S_WIDTH; i = i + 1) begin:GEN1
 697                         wire pre_first;
 698                         if (i > 0) begin:GEN2
 699                                 assign pre_first = status_found_first[i-1];
 700                         end:GEN2 else begin:GEN3
 701                                 assign pre_first = 0;
 702                         end:GEN3
 703                         assign status_found_first[i] = pre_first | S[i];
 704                         assign status_found_second[i] = pre_first & S[i];
 705                 end:GEN1
 706         endgenerate
 707
 708         \$pmux #(
 709                 .WIDTH(WIDTH),
 710                 .S_WIDTH(S_WIDTH)
 711         ) pmux_cell (
 712                 .A(A),
 713                 .B(B),
 714                 .S(S & {S_WIDTH{~|status_found_second}}),
 715                 .Y(Y)
 716         );
 717 endmodule
 718