techlibs/common/techmap.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The internal logic cell technology mapper.
  21  *
  22  *  This verilog library contains the mapping of internal cells (e.g. $not with
  23  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  24  *  gate). Usually this logic network is then mapped to the actual technology
  25  *  using e.g. the "abc" pass.
  26  *
  27  *  Note that this library does not map $mem cells. They must be mapped to logic
  28  *  and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
  29  *  which is of course highly recommended for larger memories.)
  30  *
  31  */
  32
  33 `define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
  34 `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
  35
  36
  37 // --------------------------------------------------------
  38 // Use simplemap for trivial cell types
  39 // --------------------------------------------------------
  40
  41 (* techmap_simplemap *)
  42 (* techmap_celltype = "$not $and $or $xor $xnor" *)
  43 module simplemap_bool_ops;
  44 endmodule
  45
  46 (* techmap_simplemap *)
  47 (* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
  48 module simplemap_reduce_ops;
  49 endmodule
  50
  51 (* techmap_simplemap *)
  52 (* techmap_celltype = "$logic_not $logic_and $logic_or" *)
  53 module simplemap_logic_ops;
  54 endmodule
  55
  56 (* techmap_simplemap *)
  57 (* techmap_celltype = "$pos $slice $concat $mux" *)
  58 module simplemap_various;
  59 endmodule
  60
  61 (* techmap_simplemap *)
  62 (* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
  63 module simplemap_registers;
  64 endmodule
  65
  66
  67 // --------------------------------------------------------
  68 // Trivial substitutions
  69 // --------------------------------------------------------
  70
  71 module \$neg (A, Y);
  72         parameter A_SIGNED = 0;
  73         parameter A_WIDTH = 1;
  74         parameter Y_WIDTH = 1;
  75
  76         input [A_WIDTH-1:0] A;
  77         output [Y_WIDTH-1:0] Y;
  78
  79         \$sub #(
  80                 .A_SIGNED(A_SIGNED),
  81                 .B_SIGNED(A_SIGNED),
  82                 .A_WIDTH(1),
  83                 .B_WIDTH(A_WIDTH),
  84                 .Y_WIDTH(Y_WIDTH)
  85         ) _TECHMAP_REPLACE_ (
  86                 .A(1'b0),
  87                 .B(A),
  88                 .Y(Y)
  89         );
  90 endmodule
  91
  92 module \$ge (A, B, Y);
  93         parameter A_SIGNED = 0;
  94         parameter B_SIGNED = 0;
  95         parameter A_WIDTH = 1;
  96         parameter B_WIDTH = 1;
  97         parameter Y_WIDTH = 1;
  98
  99         input [A_WIDTH-1:0] A;
 100         input [B_WIDTH-1:0] B;
 101         output [Y_WIDTH-1:0] Y;
 102
 103         \$le #(
 104                 .A_SIGNED(B_SIGNED),
 105                 .B_SIGNED(A_SIGNED),
 106                 .A_WIDTH(B_WIDTH),
 107                 .B_WIDTH(A_WIDTH),
 108                 .Y_WIDTH(Y_WIDTH)
 109         ) _TECHMAP_REPLACE_ (
 110                 .A(B),
 111                 .B(A),
 112                 .Y(Y)
 113         );
 114 endmodule
 115
 116 module \$gt (A, B, Y);
 117         parameter A_SIGNED = 0;
 118         parameter B_SIGNED = 0;
 119         parameter A_WIDTH = 1;
 120         parameter B_WIDTH = 1;
 121         parameter Y_WIDTH = 1;
 122
 123         input [A_WIDTH-1:0] A;
 124         input [B_WIDTH-1:0] B;
 125         output [Y_WIDTH-1:0] Y;
 126
 127         \$lt #(
 128                 .A_SIGNED(B_SIGNED),
 129                 .B_SIGNED(A_SIGNED),
 130                 .A_WIDTH(B_WIDTH),
 131                 .B_WIDTH(A_WIDTH),
 132                 .Y_WIDTH(Y_WIDTH)
 133         ) _TECHMAP_REPLACE_ (
 134                 .A(B),
 135                 .B(A),
 136                 .Y(Y)
 137         );
 138 endmodule
 139
 140
 141 // --------------------------------------------------------
 142 // Shift operators
 143 // --------------------------------------------------------
 144
 145 (* techmap_celltype = "$shr $shl $sshl $sshr" *)
 146 module shift_ops_shr_shl_sshl_sshr (A, B, Y);
 147         parameter A_SIGNED = 0;
 148         parameter B_SIGNED = 0;
 149         parameter A_WIDTH = 1;
 150         parameter B_WIDTH = 1;
 151         parameter Y_WIDTH = 1;
 152
 153         parameter _TECHMAP_CELLTYPE_ = "";
 154         localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 155         localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 156
 157         input [A_WIDTH-1:0] A;
 158         input [B_WIDTH-1:0] B;
 159         output [Y_WIDTH-1:0] Y;
 160
 161         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
 162         localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
 163
 164         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 165         wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 166
 167         integer i;
 168         reg [WIDTH-1:0] buffer;
 169         reg overflow;
 170
 171         always @* begin
 172                 overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
 173                 buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
 174
 175                 for (i = 0; i < BB_WIDTH; i = i+1)
 176                         if (B[i]) begin
 177                                 if (shift_left)
 178                                         buffer = {buffer, (2**i)'b0};
 179                                 else if (2**i < WIDTH)
 180                                         buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
 181                                 else
 182                                         buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
 183                         end
 184         end
 185
 186         assign Y = buffer;
 187 endmodule
 188
 189 (* techmap_celltype = "$shift $shiftx" *)
 190 module shift_shiftx (A, B, Y);
 191         parameter A_SIGNED = 0;
 192         parameter B_SIGNED = 0;
 193         parameter A_WIDTH = 1;
 194         parameter B_WIDTH = 1;
 195         parameter Y_WIDTH = 1;
 196
 197         input [A_WIDTH-1:0] A;
 198         input [B_WIDTH-1:0] B;
 199         output [Y_WIDTH-1:0] Y;
 200
 201         localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
 202         localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 203
 204         parameter _TECHMAP_CELLTYPE_ = "";
 205         localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 206
 207         wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
 208         wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;";
 209
 210         integer i;
 211         reg [WIDTH-1:0] buffer;
 212         reg overflow;
 213
 214         always @* begin
 215                 overflow = 0;
 216                 buffer = {WIDTH{extbit}};
 217                 buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
 218
 219                 if (B_WIDTH > BB_WIDTH) begin
 220                         if (B_SIGNED) begin
 221                                 for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
 222                                         if (B[i] != B[BB_WIDTH-1])
 223                                                 overflow = 1;
 224                         end else
 225                                 overflow = |B[B_WIDTH-1:BB_WIDTH];
 226                         if (overflow)
 227                                 buffer = {WIDTH{extbit}};
 228                 end
 229
 230                 for (i = BB_WIDTH-1; i >= 0; i = i-1)
 231                         if (B[i]) begin
 232                                 if (B_SIGNED && i == BB_WIDTH-1)
 233                                         buffer = {buffer, {2**i{extbit}}};
 234                                 else if (2**i < WIDTH)
 235                                         buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
 236                                 else
 237                                         buffer = {WIDTH{extbit}};
 238                         end
 239         end
 240
 241         assign Y = buffer;
 242 endmodule
 243
 244
 245 // --------------------------------------------------------
 246 // ALU Infrastructure
 247 // --------------------------------------------------------
 248
 249 module \$fa (A, B, C, X, Y);
 250         parameter WIDTH = 1;
 251
 252         input [WIDTH-1:0] A, B, C;
 253         output [WIDTH-1:0] X, Y;
 254
 255         wire [WIDTH-1:0] t1, t2, t3;
 256
 257         assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
 258         assign Y = t1 ^ C, X = t2 | t3;
 259 endmodule
 260
 261 module \$__alu_ripple (A, B, CI, X, Y, CO);
 262         parameter WIDTH = 1;
 263
 264         input [WIDTH-1:0] A, B;
 265         output [WIDTH-1:0] X, Y;
 266
 267         input CI;
 268         output [WIDTH-1:0] CO;
 269
 270         wire [WIDTH:0] carry;
 271         assign carry[0] = CI;
 272         assign CO = carry[WIDTH:1];
 273
 274         genvar i;
 275         generate
 276                 for (i = 0; i < WIDTH; i = i+1)
 277                 begin:V
 278                         // {x, y} = a + b + c
 279                         wire a, b, c, x, y;
 280                         wire t1, t2, t3;
 281
 282                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(t1) );
 283                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(t2) );
 284                         \$_AND_ gate3 ( .A(t2), .B(c),  .Y(t3) );
 285                         \$_XOR_ gate4 ( .A(t2), .B(c),  .Y(y)  );
 286                         \$_OR_  gate5 ( .A(t1), .B(t3), .Y(x)  );
 287
 288                         assign a = A[i], b = B[i], c = carry[i];
 289                         assign carry[i+1] = x, X[i] = t2, Y[i] = y;
 290                 end
 291         endgenerate
 292 endmodule
 293
 294 module \$__lcu (P, G, CI, CO);
 295         parameter WIDTH = 2;
 296
 297         input [WIDTH-1:0] P, G;
 298         input CI;
 299
 300         output [WIDTH-1:0] CO;
 301
 302         integer i, j;
 303         reg [WIDTH-1:0] p, g;
 304
 305         wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
 306
 307         always @* begin
 308                 p = P;
 309                 g = G;
 310
 311                 // in almost all cases CI will be constant zero
 312                 g[0] = g[0] | (p[0] & CI);
 313
 314                 // [[CITE]] Brent Kung Adder
 315                 // R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
 316                 // IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
 317
 318                 // Main tree
 319                 for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
 320                         for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
 321                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 322                                 p[j] = p[j] & p[j - 2**(i-1)];
 323                         end
 324                 end
 325
 326                 // Inverse tree
 327                 for (i = $clog2(WIDTH); i > 0; i = i-1) begin
 328                         for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
 329                                 g[j] = g[j] | p[j] & g[j - 2**(i-1)];
 330                                 p[j] = p[j] & p[j - 2**(i-1)];
 331                         end
 332                 end
 333         end
 334
 335         assign CO = g;
 336 endmodule
 337
 338 module \$__alu_lookahead (A, B, CI, X, Y, CO);
 339         parameter WIDTH = 1;
 340
 341         input [WIDTH-1:0] A, B;
 342         output [WIDTH-1:0] X, Y;
 343
 344         input CI;
 345         output [WIDTH-1:0] CO;
 346
 347         wire [WIDTH-1:0] P, G;
 348         wire [WIDTH:0] carry;
 349
 350         genvar i;
 351         generate
 352                 for (i = 0; i < WIDTH; i = i+1)
 353                 begin:V
 354                         wire a, b, c, p, g, y;
 355
 356                         \$_AND_ gate1 ( .A(a),  .B(b),  .Y(g) );
 357                         \$_XOR_ gate2 ( .A(a),  .B(b),  .Y(p) );
 358                         \$_XOR_ gate3 ( .A(p),  .B(c),  .Y(y) );
 359
 360                         assign a = A[i], b = B[i], c = carry[i];
 361                         assign P[i] = p, G[i] = g, X[i] = p, Y[i] = y;
 362                 end
 363         endgenerate
 364
 365         \$__lcu #(.WIDTH(WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO));
 366         assign carry = {CO, CI};
 367 endmodule
 368
 369 module \$alu (A, B, CI, BI, X, Y, CO);
 370         parameter A_SIGNED = 0;
 371         parameter B_SIGNED = 0;
 372         parameter A_WIDTH = 1;
 373         parameter B_WIDTH = 1;
 374         parameter Y_WIDTH = 1;
 375
 376         input [A_WIDTH-1:0] A;
 377         input [B_WIDTH-1:0] B;
 378         output [Y_WIDTH-1:0] X, Y;
 379
 380         input CI, BI;
 381         output [Y_WIDTH-1:0] CO;
 382
 383         wire [Y_WIDTH-1:0] A_buf, B_buf;
 384         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 385         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 386
 387 `ifdef ALU_RIPPLE
 388         \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 389 `else
 390         if (Y_WIDTH <= 4) begin
 391                 \$__alu_ripple #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 392         end else begin
 393                 \$__alu_lookahead #(.WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_buf), .B(BI ? ~B_buf : B_buf), .CI(CI), .X(X), .Y(Y), .CO(CO));
 394         end
 395 `endif
 396 endmodule
 397
 398
 399 // --------------------------------------------------------
 400 // ALU Cell Types: Compare, Add, Subtract
 401 // --------------------------------------------------------
 402
 403 `define ALU_COMMONS(_width, _sub) """
 404         parameter A_SIGNED = 0;
 405         parameter B_SIGNED = 0;
 406         parameter A_WIDTH = 1;
 407         parameter B_WIDTH = 1;
 408         parameter Y_WIDTH = 1;
 409
 410         localparam WIDTH = _width;
 411
 412         input [A_WIDTH-1:0] A;
 413         input [B_WIDTH-1:0] B;
 414         output [Y_WIDTH-1:0] Y;
 415
 416         wire [WIDTH-1:0] alu_x, alu_y, alu_co;
 417         wire [WIDTH:0] carry = {alu_co, |_sub};
 418
 419         \$alu #(
 420                 .A_SIGNED(A_SIGNED),
 421                 .B_SIGNED(B_SIGNED),
 422                 .A_WIDTH(A_WIDTH),
 423                 .B_WIDTH(B_WIDTH),
 424                 .Y_WIDTH(WIDTH)
 425         ) alu (
 426                 .A(A),
 427                 .B(B),
 428                 .CI(|_sub),
 429                 .BI(|_sub),
 430                 .X(alu_x),
 431                 .Y(alu_y),
 432                 .CO(alu_co)
 433         );
 434
 435         wire cf, of, zf, sf;
 436         assign cf = !carry[WIDTH];
 437         assign of = carry[WIDTH] ^ carry[WIDTH-1];
 438         assign sf = alu_y[WIDTH-1];
 439 """
 440
 441 module \$lt (A, B, Y);
 442         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 443         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 444         assign Y = A_SIGNED && B_SIGNED ? of != sf : cf;
 445 endmodule
 446
 447 module \$le (A, B, Y);
 448         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 449         `ALU_COMMONS(`MAX(A_WIDTH, B_WIDTH), 1)
 450         assign Y = &alu_x || (A_SIGNED && B_SIGNED ? of != sf : cf);
 451 endmodule
 452
 453 module \$add (A, B, Y);
 454         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 455         `ALU_COMMONS(Y_WIDTH, 0)
 456         assign Y = alu_y;
 457 endmodule
 458
 459 module \$sub (A, B, Y);
 460         wire [1023:0] _TECHMAP_DO_ = "RECURSION; opt_const -mux_undef -mux_bool -fine;;;";
 461         `ALU_COMMONS(Y_WIDTH, 1)
 462         assign Y = alu_y;
 463 endmodule
 464
 465
 466 // --------------------------------------------------------
 467 // Multiply
 468 // --------------------------------------------------------
 469
 470 (* techmap_maccmap *)
 471 module \$macc ;
 472 endmodule
 473
 474 module \$mul (A, B, Y);
 475         parameter A_SIGNED = 0;
 476         parameter B_SIGNED = 0;
 477         parameter A_WIDTH = 1;
 478         parameter B_WIDTH = 1;
 479         parameter Y_WIDTH = 1;
 480
 481         input [A_WIDTH-1:0] A;
 482         input [B_WIDTH-1:0] B;
 483         output [Y_WIDTH-1:0] Y;
 484
 485         wire [1023:0] _TECHMAP_DO_ = "RECURSION; CONSTMAP; opt -purge";
 486
 487         localparam [ 3:0] CONFIG_WIDTH_BITS = 15;
 488         localparam [ 0:0] CONFIG_IS_SIGNED = A_SIGNED && B_SIGNED;
 489         localparam [ 0:0] CONFIG_DO_SUBTRACT = 0;
 490         localparam [14:0] CONFIG_A_WIDTH = A_WIDTH;
 491         localparam [14:0] CONFIG_B_WIDTH = B_WIDTH;
 492
 493         \$macc #(
 494                 .CONFIG({CONFIG_B_WIDTH, CONFIG_A_WIDTH, CONFIG_DO_SUBTRACT, CONFIG_IS_SIGNED, CONFIG_WIDTH_BITS}),
 495                 .CONFIG_WIDTH(15 + 15 + 2 + 4),
 496                 .A_WIDTH(B_WIDTH + A_WIDTH),
 497                 .B_WIDTH(0),
 498                 .Y_WIDTH(Y_WIDTH)
 499         ) _TECHMAP_REPLACE_ (
 500                 .A({B, A}),
 501                 .B(),
 502                 .Y(Y)
 503         );
 504 endmodule
 505
 506
 507 // --------------------------------------------------------
 508 // Divide and Modulo
 509 // --------------------------------------------------------
 510
 511 module \$__div_mod_u (A, B, Y, R);
 512         parameter WIDTH = 1;
 513
 514         input [WIDTH-1:0] A, B;
 515         output [WIDTH-1:0] Y, R;
 516
 517         wire [WIDTH*WIDTH-1:0] chaindata;
 518         assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 519
 520         genvar i;
 521         generate begin
 522                 for (i = 0; i < WIDTH; i=i+1) begin:stage
 523                         wire [WIDTH-1:0] stage_in;
 524
 525                         if (i == 0) begin:cp
 526                                 assign stage_in = A;
 527                         end else begin:cp
 528                                 assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
 529                         end
 530
 531                         assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
 532                         assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
 533                 end
 534         end endgenerate
 535 endmodule
 536
 537 module \$__div_mod (A, B, Y, R);
 538         parameter A_SIGNED = 0;
 539         parameter B_SIGNED = 0;
 540         parameter A_WIDTH = 1;
 541         parameter B_WIDTH = 1;
 542         parameter Y_WIDTH = 1;
 543
 544         localparam WIDTH =
 545                         A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 546                         B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 547
 548         input [A_WIDTH-1:0] A;
 549         input [B_WIDTH-1:0] B;
 550         output [Y_WIDTH-1:0] Y, R;
 551
 552         wire [WIDTH-1:0] A_buf, B_buf;
 553         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 554         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 555
 556         wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 557         assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 558         assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
 559
 560         \$__div_mod_u #(
 561                 .WIDTH(WIDTH)
 562         ) div_mod_u (
 563                 .A(A_buf_u),
 564                 .B(B_buf_u),
 565                 .Y(Y_u),
 566                 .R(R_u)
 567         );
 568
 569         assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
 570         assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
 571 endmodule
 572
 573 module \$div (A, B, Y);
 574         parameter A_SIGNED = 0;
 575         parameter B_SIGNED = 0;
 576         parameter A_WIDTH = 1;
 577         parameter B_WIDTH = 1;
 578         parameter Y_WIDTH = 1;
 579
 580         input [A_WIDTH-1:0] A;
 581         input [B_WIDTH-1:0] B;
 582         output [Y_WIDTH-1:0] Y;
 583
 584         \$__div_mod #(
 585                 .A_SIGNED(A_SIGNED),
 586                 .B_SIGNED(B_SIGNED),
 587                 .A_WIDTH(A_WIDTH),
 588                 .B_WIDTH(B_WIDTH),
 589                 .Y_WIDTH(Y_WIDTH)
 590         ) div_mod (
 591                 .A(A),
 592                 .B(B),
 593                 .Y(Y)
 594         );
 595 endmodule
 596
 597 module \$mod (A, B, Y);
 598         parameter A_SIGNED = 0;
 599         parameter B_SIGNED = 0;
 600         parameter A_WIDTH = 1;
 601         parameter B_WIDTH = 1;
 602         parameter Y_WIDTH = 1;
 603
 604         input [A_WIDTH-1:0] A;
 605         input [B_WIDTH-1:0] B;
 606         output [Y_WIDTH-1:0] Y;
 607
 608         \$__div_mod #(
 609                 .A_SIGNED(A_SIGNED),
 610                 .B_SIGNED(B_SIGNED),
 611                 .A_WIDTH(A_WIDTH),
 612                 .B_WIDTH(B_WIDTH),
 613                 .Y_WIDTH(Y_WIDTH)
 614         ) div_mod (
 615                 .A(A),
 616                 .B(B),
 617                 .R(Y)
 618         );
 619 endmodule
 620
 621
 622 // --------------------------------------------------------
 623 // Power
 624 // --------------------------------------------------------
 625
 626 module \$pow (A, B, Y);
 627         parameter A_SIGNED = 0;
 628         parameter B_SIGNED = 0;
 629         parameter A_WIDTH = 1;
 630         parameter B_WIDTH = 1;
 631         parameter Y_WIDTH = 1;
 632
 633         input [A_WIDTH-1:0] A;
 634         input [B_WIDTH-1:0] B;
 635         output [Y_WIDTH-1:0] Y;
 636
 637         wire _TECHMAP_FAIL_ = 1;
 638 endmodule
 639
 640
 641 // --------------------------------------------------------
 642 // Equal and Not-Equal
 643 // --------------------------------------------------------
 644
 645 module \$eq (A, B, Y);
 646         parameter A_SIGNED = 0;
 647         parameter B_SIGNED = 0;
 648         parameter A_WIDTH = 1;
 649         parameter B_WIDTH = 1;
 650         parameter Y_WIDTH = 1;
 651
 652         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 653
 654         input [A_WIDTH-1:0] A;
 655         input [B_WIDTH-1:0] B;
 656         output [Y_WIDTH-1:0] Y;
 657
 658         wire carry, carry_sign;
 659         wire [WIDTH-1:0] A_buf, B_buf;
 660         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 661         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 662
 663         assign Y = ~|(A_buf ^ B_buf);
 664 endmodule
 665
 666 module \$ne (A, B, Y);
 667         parameter A_SIGNED = 0;
 668         parameter B_SIGNED = 0;
 669         parameter A_WIDTH = 1;
 670         parameter B_WIDTH = 1;
 671         parameter Y_WIDTH = 1;
 672
 673         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 674
 675         input [A_WIDTH-1:0] A;
 676         input [B_WIDTH-1:0] B;
 677         output [Y_WIDTH-1:0] Y;
 678
 679         wire carry, carry_sign;
 680         wire [WIDTH-1:0] A_buf, B_buf;
 681         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 682         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 683
 684         assign Y = |(A_buf ^ B_buf);
 685 endmodule
 686
 687 module \$eqx (A, B, Y);
 688         parameter A_SIGNED = 0;
 689         parameter B_SIGNED = 0;
 690         parameter A_WIDTH = 1;
 691         parameter B_WIDTH = 1;
 692         parameter Y_WIDTH = 1;
 693
 694         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 695
 696         input [A_WIDTH-1:0] A;
 697         input [B_WIDTH-1:0] B;
 698         output [Y_WIDTH-1:0] Y;
 699
 700         wire carry, carry_sign;
 701         wire [WIDTH-1:0] A_buf, B_buf;
 702         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 703         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 704
 705         assign Y = ~|(A_buf ^ B_buf);
 706 endmodule
 707
 708 module \$nex (A, B, Y);
 709         parameter A_SIGNED = 0;
 710         parameter B_SIGNED = 0;
 711         parameter A_WIDTH = 1;
 712         parameter B_WIDTH = 1;
 713         parameter Y_WIDTH = 1;
 714
 715         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
 716
 717         input [A_WIDTH-1:0] A;
 718         input [B_WIDTH-1:0] B;
 719         output [Y_WIDTH-1:0] Y;
 720
 721         wire carry, carry_sign;
 722         wire [WIDTH-1:0] A_buf, B_buf;
 723         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 724         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 725
 726         assign Y = |(A_buf ^ B_buf);
 727 endmodule
 728
 729
 730 // --------------------------------------------------------
 731 // Parallel Multiplexers
 732 // --------------------------------------------------------
 733
 734 module \$pmux (A, B, S, Y);
 735         parameter WIDTH = 1;
 736         parameter S_WIDTH = 1;
 737
 738         input [WIDTH-1:0] A;
 739         input [WIDTH*S_WIDTH-1:0] B;
 740         input [S_WIDTH-1:0] S;
 741         output [WIDTH-1:0] Y;
 742
 743         wire [WIDTH-1:0] Y_B;
 744
 745         genvar i, j;
 746         generate
 747                 wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 748                 for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 749                         assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 750                 end:B_AND
 751                 for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
 752                         wire [S_WIDTH-1:0] B_AND_BITS;
 753                         for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 754                                 assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
 755                         end:B_AND_BITS_COLLECT
 756                         assign Y_B[i] = |B_AND_BITS;
 757                 end:B_OR
 758         endgenerate
 759
 760         assign Y = |S ? Y_B : A;
 761 endmodule
 762
 763
 764 // --------------------------------------------------------
 765 // LUTs
 766 // --------------------------------------------------------
 767
 768 `ifndef NOLUT
 769 module \$lut (A, Y);
 770         parameter WIDTH = 1;
 771         parameter LUT = 0;
 772
 773         input [WIDTH-1:0] A;
 774         output Y;
 775
 776         assign Y = LUT[A];
 777 endmodule
 778 `endif
 779