techlibs/coolrunner2/cells_sim.v

   1 module IBUF(input I, output O);
   2     assign O = I;
   3 endmodule
   4
   5 module IOBUFE(input I, input E, output O, inout IO);
   6     assign O = IO;
   7     assign IO = E ? I : 1'bz;
   8 endmodule
   9
  10 module ANDTERM(IN, IN_B, OUT);
  11     parameter TRUE_INP = 0;
  12     parameter COMP_INP = 0;
  13
  14     input [TRUE_INP-1:0] IN;
  15     input [COMP_INP-1:0] IN_B;
  16     output reg OUT;
  17
  18     integer i;
  19
  20     always @(*) begin
  21         OUT = 1;
  22         for (i = 0; i < TRUE_INP; i=i+1)
  23             OUT = OUT & IN[i];
  24         for (i = 0; i < COMP_INP; i=i+1)
  25             OUT = OUT & ~IN_B[i];
  26     end
  27 endmodule
  28
  29 module ORTERM(IN, OUT);
  30     parameter WIDTH = 0;
  31
  32     input [WIDTH-1:0] IN;
  33     output reg OUT;
  34
  35     integer i;
  36
  37     always @(*) begin
  38         OUT = 0;
  39         for (i = 0; i < WIDTH; i=i+1) begin
  40             OUT = OUT | IN[i];
  41         end
  42     end
  43 endmodule
  44
  45 module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
  46     parameter INVERT_OUT = 0;
  47
  48     input IN_PTC;
  49     input IN_ORTERM;
  50     output wire OUT;
  51
  52     wire xor_intermed;
  53
  54     assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
  55     assign xor_intermed = IN_ORTERM ^ IN_PTC;
  56 endmodule
  57
  58 module FDCP (C, PRE, CLR, D, Q);
  59     parameter INIT = 0;
  60
  61     input C, PRE, CLR, D;
  62     output reg Q;
  63
  64     initial begin
  65         Q <= INIT;
  66     end
  67
  68     always @(posedge C, posedge PRE, posedge CLR) begin
  69         if (CLR == 1)
  70             Q <= 0;
  71         else if (PRE == 1)
  72             Q <= 1;
  73         else
  74             Q <= D;
  75     end
  76 endmodule
  77
  78 module FDCP_N (C, PRE, CLR, D, Q);
  79     parameter INIT = 0;
  80
  81     input C, PRE, CLR, D;
  82     output reg Q;
  83
  84     initial begin
  85         Q <= INIT;
  86     end
  87
  88     always @(negedge C, posedge PRE, posedge CLR) begin
  89         if (CLR == 1)
  90             Q <= 0;
  91         else if (PRE == 1)
  92             Q <= 1;
  93         else
  94             Q <= D;
  95     end
  96 endmodule
  97
  98 module LDCP (G, PRE, CLR, D, Q);
  99     parameter INIT = 0;
 100
 101     input G, PRE, CLR, D;
 102     output reg Q;
 103
 104     initial begin
 105         Q <= INIT;
 106     end
 107
 108     always @* begin
 109         if (CLR == 1)
 110             Q <= 0;
 111         else if (G == 1)
 112             Q <= D;
 113         else if (PRE == 1)
 114             Q <= 1;
 115     end
 116 endmodule
 117
 118 module LDCP_N (G, PRE, CLR, D, Q);
 119     parameter INIT = 0;
 120
 121     input G, PRE, CLR, D;
 122     output reg Q;
 123
 124     initial begin
 125         Q <= INIT;
 126     end
 127
 128     always @* begin
 129         if (CLR == 1)
 130             Q <= 0;
 131         else if (G == 0)
 132             Q <= D;
 133         else if (PRE == 1)
 134             Q <= 1;
 135     end
 136 endmodule
 137
 138 module BUFG(I, O);
 139     input I;
 140     output O;
 141
 142     assign O = I;
 143 endmodule
 144
 145 module BUFGSR(I, O);
 146     parameter INVERT = 0;
 147
 148     input I;
 149     output O;
 150
 151     assign O = INVERT ? ~I : I;
 152 endmodule
 153
 154 module BUFGTS(I, O);
 155     parameter INVERT = 0;
 156
 157     input I;
 158     output O;
 159
 160     assign O = INVERT ? ~I : I;
 161 endmodule
 162
 163 module FDDCP (C, PRE, CLR, D, Q);
 164     parameter INIT = 0;
 165
 166     input C, PRE, CLR, D;
 167     output reg Q;
 168
 169     initial begin
 170         Q <= INIT;
 171     end
 172
 173     always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
 174         if (CLR == 1)
 175             Q <= 0;
 176         else if (PRE == 1)
 177             Q <= 1;
 178         else
 179             Q <= D;
 180     end
 181 endmodule
 182
 183 module FTCP (C, PRE, CLR, T, Q);
 184     parameter INIT = 0;
 185
 186     input C, PRE, CLR, T;
 187     output wire Q;
 188     reg Q_;
 189
 190     initial begin
 191         Q_ <= INIT;
 192     end
 193
 194     always @(posedge C, posedge PRE, posedge CLR) begin
 195         if (CLR == 1)
 196             Q_ <= 0;
 197         else if (PRE == 1)
 198             Q_ <= 1;
 199         else if (T == 1)
 200             Q_ <= ~Q_;
 201     end
 202
 203     assign Q = Q_;
 204 endmodule
 205
 206 module FTCP_N (C, PRE, CLR, T, Q);
 207     parameter INIT = 0;
 208
 209     input C, PRE, CLR, T;
 210     output wire Q;
 211     reg Q_;
 212
 213     initial begin
 214         Q_ <= INIT;
 215     end
 216
 217     always @(negedge C, posedge PRE, posedge CLR) begin
 218         if (CLR == 1)
 219             Q_ <= 0;
 220         else if (PRE == 1)
 221             Q_ <= 1;
 222         else if (T == 1)
 223             Q_ <= ~Q_;
 224     end
 225
 226     assign Q = Q_;
 227 endmodule
 228
 229 module FTDCP (C, PRE, CLR, T, Q);
 230     parameter INIT = 0;
 231
 232     input C, PRE, CLR, T;
 233     output wire Q;
 234     reg Q_;
 235
 236     initial begin
 237         Q_ <= INIT;
 238     end
 239
 240     always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
 241         if (CLR == 1)
 242             Q_ <= 0;
 243         else if (PRE == 1)
 244             Q_ <= 1;
 245         else if (T == 1)
 246             Q_ <= ~Q_;
 247     end
 248
 249     assign Q = Q_;
 250 endmodule
 251
 252 module FDCPE (C, PRE, CLR, D, Q, CE);
 253     parameter INIT = 0;
 254
 255     input C, PRE, CLR, D, CE;
 256     output reg Q;
 257
 258     initial begin
 259         Q <= INIT;
 260     end
 261
 262     always @(posedge C, posedge PRE, posedge CLR) begin
 263         if (CLR == 1)
 264             Q <= 0;
 265         else if (PRE == 1)
 266             Q <= 1;
 267         else if (CE == 1)
 268             Q <= D;
 269     end
 270 endmodule
 271
 272 module FDCPE_N (C, PRE, CLR, D, Q, CE);
 273     parameter INIT = 0;
 274
 275     input C, PRE, CLR, D, CE;
 276     output reg Q;
 277
 278     initial begin
 279         Q <= INIT;
 280     end
 281
 282     always @(negedge C, posedge PRE, posedge CLR) begin
 283         if (CLR == 1)
 284             Q <= 0;
 285         else if (PRE == 1)
 286             Q <= 1;
 287         else if (CE == 1)
 288             Q <= D;
 289     end
 290 endmodule
 291
 292 module FDDCPE (C, PRE, CLR, D, Q, CE);
 293     parameter INIT = 0;
 294
 295     input C, PRE, CLR, D, CE;
 296     output reg Q;
 297
 298     initial begin
 299         Q <= INIT;
 300     end
 301
 302     always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
 303         if (CLR == 1)
 304             Q <= 0;
 305         else if (PRE == 1)
 306             Q <= 1;
 307         else if (CE == 1)
 308             Q <= D;
 309     end
 310 endmodule