2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2017 Robert Ou <rqou@robertou.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthCoolrunner2Pass
: public ScriptPass
30 SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth_coolrunner2 [options]\n");
38 log("This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.\n");
39 log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
40 log("place-and-route.\n");
42 log(" -top <module>\n");
43 log(" use the specified module as top module (default='top')\n");
45 log(" -json <file>\n");
46 log(" write the design to the specified JSON file. writing of an output file\n");
47 log(" is omitted if this parameter is not specified.\n");
49 log(" -run <from_label>:<to_label>\n");
50 log(" only run the commands between the labels (see below). an empty\n");
51 log(" from label is synonymous to 'begin', and empty to label is\n");
52 log(" synonymous to the end of the command list.\n");
55 log(" do not flatten design before synthesis\n");
58 log(" run 'abc' with '-dff -D 1' options\n");
61 log("The following commands are executed by this synthesis command:\n");
66 string top_opt
, json_file
;
69 void clear_flags() YS_OVERRIDE
71 top_opt
= "-auto-top";
77 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
79 string run_from
, run_to
;
83 for (argidx
= 1; argidx
< args
.size(); argidx
++)
85 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
86 top_opt
= "-top " + args
[++argidx
];
89 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
90 json_file
= args
[++argidx
];
93 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
94 size_t pos
= args
[argidx
+1].find(':');
95 if (pos
== std::string::npos
)
97 run_from
= args
[++argidx
].substr(0, pos
);
98 run_to
= args
[argidx
].substr(pos
+1);
101 if (args
[argidx
] == "-noflatten") {
105 if (args
[argidx
] == "-retime") {
111 extra_args(args
, argidx
, design
);
113 if (!design
->full_selection())
114 log_cmd_error("This command only operates on fully selected designs!\n");
116 log_header(design
, "Executing SYNTH_COOLRUNNER2 pass.\n");
119 run_script(design
, run_from
, run_to
);
124 void script() YS_OVERRIDE
126 if (check_label("begin"))
128 run("read_verilog -lib +/coolrunner2/cells_sim.v");
129 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
132 if (flatten
&& check_label("flatten", "(unless -noflatten)"))
136 run("tribuf -logic");
139 if (check_label("coarse"))
141 run("synth -run coarse");
144 if (check_label("fine"))
146 run("opt -fast -full");
148 run("techmap -map +/coolrunner2/cells_latch.v");
149 run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
152 if (check_label("map_tff"))
154 // This is quite hacky. By telling abc that it can only use AND and XOR gates, abc will try and use XOR
155 // gates "whenever possible." This will hopefully cause toggle flip-flop structures to turn into an XOR
156 // connected to a D flip-flop. We then match on these and convert them into XC2 TFF cells.
157 run("abc -g AND,XOR");
159 run("extract -map +/coolrunner2/tff_extract.v");
162 if (check_label("map_pla"))
164 run("abc -sop -I 40 -P 56" + string(retime
? " -dff -D 1" : ""));
168 if (check_label("map_cells"))
170 run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
171 run("dffinit -ff FDCP Q INIT");
172 run("dffinit -ff FDCP_N Q INIT");
173 run("dffinit -ff FTCP Q INIT");
174 run("dffinit -ff FTCP_N Q INIT");
175 run("dffinit -ff LDCP Q INIT");
176 run("dffinit -ff LDCP_N Q INIT");
177 run("coolrunner2_sop");
178 run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
179 run("attrmvcp -attr src -attr LOC t:IOBUFE n:*");
180 run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");
185 if (check_label("check"))
187 run("hierarchy -check");
189 run("check -noinit");
192 if (check_label("json"))
194 if (!json_file
.empty() || help_mode
)
195 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
198 } SynthCoolrunner2Pass
;
200 PRIVATE_NAMESPACE_END