techlibs/coolrunner2/synth_coolrunner2.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2017 Robert Ou <rqou@robertou.com>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthCoolrunner2Pass : public ScriptPass
  29 {
  30         SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_coolrunner2 [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.\n");
  39                 log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
  40                 log("place-and-route.\n");
  41                 log("\n");
  42                 log("    -top <module>\n");
  43                 log("        use the specified module as top module (default='top')\n");
  44                 log("\n");
  45                 log("    -json <file>\n");
  46                 log("        write the design to the specified JSON file. writing of an output file\n");
  47                 log("        is omitted if this parameter is not specified.\n");
  48                 log("\n");
  49                 log("    -run <from_label>:<to_label>\n");
  50                 log("        only run the commands between the labels (see below). an empty\n");
  51                 log("        from label is synonymous to 'begin', and empty to label is\n");
  52                 log("        synonymous to the end of the command list.\n");
  53                 log("\n");
  54                 log("    -noflatten\n");
  55                 log("        do not flatten design before synthesis\n");
  56                 log("\n");
  57                 log("    -retime\n");
  58                 log("        run 'abc' with '-dff -D 1' options\n");
  59                 log("\n");
  60                 log("\n");
  61                 log("The following commands are executed by this synthesis command:\n");
  62                 help_script();
  63                 log("\n");
  64         }
  65
  66         string top_opt, json_file;
  67         bool flatten, retime;
  68
  69         void clear_flags() YS_OVERRIDE
  70         {
  71                 top_opt = "-auto-top";
  72                 json_file = "";
  73                 flatten = true;
  74                 retime = false;
  75         }
  76
  77         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  78         {
  79                 string run_from, run_to;
  80                 clear_flags();
  81
  82                 size_t argidx;
  83                 for (argidx = 1; argidx < args.size(); argidx++)
  84                 {
  85                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
  86                                 top_opt = "-top " + args[++argidx];
  87                                 continue;
  88                         }
  89                         if (args[argidx] == "-json" && argidx+1 < args.size()) {
  90                                 json_file = args[++argidx];
  91                                 continue;
  92                         }
  93                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
  94                                 size_t pos = args[argidx+1].find(':');
  95                                 if (pos == std::string::npos)
  96                                         break;
  97                                 run_from = args[++argidx].substr(0, pos);
  98                                 run_to = args[argidx].substr(pos+1);
  99                                 continue;
 100                         }
 101                         if (args[argidx] == "-noflatten") {
 102                                 flatten = false;
 103                                 continue;
 104                         }
 105                         if (args[argidx] == "-retime") {
 106                                 retime = true;
 107                                 continue;
 108                         }
 109                         break;
 110                 }
 111                 extra_args(args, argidx, design);
 112
 113                 if (!design->full_selection())
 114                         log_cmd_error("This command only operates on fully selected designs!\n");
 115
 116                 log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
 117                 log_push();
 118
 119                 run_script(design, run_from, run_to);
 120
 121                 log_pop();
 122         }
 123
 124         void script() YS_OVERRIDE
 125         {
 126                 if (check_label("begin"))
 127                 {
 128                         run("read_verilog -lib +/coolrunner2/cells_sim.v");
 129                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 130                 }
 131
 132                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 133                 {
 134                         run("proc");
 135                         run("flatten");
 136                         run("tribuf -logic");
 137                 }
 138
 139                 if (check_label("coarse"))
 140                 {
 141                         run("synth -run coarse");
 142                 }
 143
 144                 if (check_label("fine"))
 145                 {
 146                         run("opt -fast -full");
 147                         run("techmap -map +/techmap.v -map +/coolrunner2/cells_latch.v");
 148                         run("opt -fast");
 149                         run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
 150                 }
 151
 152                 if (check_label("map_tff"))
 153                 {
 154                         // This is quite hacky. By telling abc that it can only use AND and XOR gates, abc will try and use XOR
 155                         // gates "whenever possible." This will hopefully cause toggle flip-flop structures to turn into an XOR
 156                         // connected to a D flip-flop. We then match on these and convert them into XC2 TFF cells.
 157                         run("abc -g AND,XOR");
 158                         run("clean");
 159                         run("extract -map +/coolrunner2/tff_extract.v");
 160                 }
 161
 162                 if (check_label("map_pla"))
 163                 {
 164                         run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
 165                         run("clean");
 166                 }
 167
 168                 if (check_label("map_cells"))
 169                 {
 170                         run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
 171                         run("dffinit -ff FDCP Q INIT");
 172                         run("dffinit -ff FDCP_N Q INIT");
 173                         run("dffinit -ff FTCP Q INIT");
 174                         run("dffinit -ff FTCP_N Q INIT");
 175                         run("dffinit -ff LDCP Q INIT");
 176                         run("dffinit -ff LDCP_N Q INIT");
 177                         run("coolrunner2_sop");
 178                         run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
 179                         run("attrmvcp -attr src -attr LOC t:IOBUFE n:*");
 180                         run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");
 181                         run("splitnets");
 182                         run("clean");
 183                 }
 184
 185                 if (check_label("check"))
 186                 {
 187                         run("hierarchy -check");
 188                         run("stat");
 189                         run("check -noinit");
 190                 }
 191
 192                 if (check_label("json"))
 193                 {
 194                         if (!json_file.empty() || help_mode)
 195                                 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
 196                 }
 197         }
 198 } SynthCoolrunner2Pass;
 199
 200 PRIVATE_NAMESPACE_END