1 # NB: Box inputs/outputs must each be in the same order
2 # as their corresponding module definition
3 # (with exceptions detailed below)
5 # Box 1 : CCU2C (2xCARRY + 2xLUT4)
6 # (Exception: carry chain input/output must be the
7 # last input and output and the entire bus has been
8 # moved there overriding the otherwise
9 # alphabetical ordering)
10 # name ID w/b ins outs
12 #A0 B0 C0 D0 A1 B1 C1 D1 CIN
13 379 379 275 141 - - - - 257 # S0
14 630 630 526 392 379 379 275 141 273 # S1
15 516 516 412 278 516 516 412 278 43 # COUT
17 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
18 # name ID w/b ins outs
19 $__ABC9_DPR16X4_COMB 2 0 8 4
20 #$DO0 $DO1 $DO2 $DO3 RAD0 RAD1 RAD2 RAD3
21 0 0 0 0 141 379 275 379 # DO0
22 0 0 0 0 141 379 275 379 # DO1
23 0 0 0 0 141 379 275 379 # DO2
24 0 0 0 0 141 379 275 379 # DO3
26 # Box 3 : PFUMX (MUX2)
27 # name ID w/b ins outs
32 # Box 4 : L6MUX21 (MUX2)
33 # name ID w/b ins outs