Merge pull request #1559 from YosysHQ/efinix_test_fix
[yosys.git] / techlibs / ecp5 / abc9_5g.lut
1 # ECP5-5G LUT library for ABC
2 # Note that ECP5 architecture assigns difference
3 # in LUT input delay to interconnect, so this is
4 # considered too
5
6
7 # Simple LUTs
8 # area D C B A
9 1 1 141
10 2 1 141 275
11 3 1 141 275 379
12 4 1 141 275 379 379
13
14 # LUT5 = 2x LUT4 + PFUMX
15 # area M0 D C B A
16 5 2 151 239 373 477 477
17
18 # LUT6 = 2x LUT5 + MUX2
19 # area M1 M0 D C B A
20 6 4 148 292 380 514 618 618
21
22 # LUT7 = 2x LUT6 + MUX2
23 # area M2 M1 M0 D C B A
24 7 8 148 289 433 521 655 759 759
25