Remove peepopt call in synth_xilinx since already in synth -run coarse
[yosys.git] / techlibs / ecp5 / abc_5g_nowide.lut
1 # ECP5-5G LUT library for ABC
2 # Note that ECP5 architecture assigns difference
3 # in LUT input delay to interconnect, so this is
4 # considered too
5
6
7 # Simple LUTs
8 # area D C B A
9 1 1 141
10 2 1 141 275
11 3 1 141 275 379
12 4 1 141 275 379 379