techlibs/ecp5/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *  Copyright (C) 2018  David Shah <dave@ds0.me>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 (* techmap_celltype = "$alu" *)
  22 module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
  23         parameter A_SIGNED = 0;
  24         parameter B_SIGNED = 0;
  25         parameter A_WIDTH = 1;
  26         parameter B_WIDTH = 1;
  27         parameter Y_WIDTH = 1;
  28
  29         input [A_WIDTH-1:0] A;
  30         input [B_WIDTH-1:0] B;
  31         output [Y_WIDTH-1:0] X, Y;
  32
  33         input CI, BI;
  34         output [Y_WIDTH-1:0] CO;
  35
  36         wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
  37
  38         wire [Y_WIDTH-1:0] A_buf, B_buf;
  39         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
  40         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
  41
  42         function integer round_up2;
  43                 input integer N;
  44                 begin
  45                         round_up2 = ((N + 1) / 2) * 2;
  46                 end
  47         endfunction
  48
  49         localparam Y_WIDTH2 = round_up2(Y_WIDTH);
  50
  51         wire [Y_WIDTH2-1:0] AA = A_buf;
  52         wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
  53         wire [Y_WIDTH2-1:0] C = {CO, CI};
  54         wire [Y_WIDTH2-1:0] FCO, Y1;
  55
  56         genvar i;
  57         generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
  58                 CCU2C #(
  59                         .INIT0(16'b0110011010101010),
  60                         .INIT1(16'b0110011010101010),
  61                         .INJECT1_0("NO"),
  62                         .INJECT1_1("NO")
  63            ) ccu2c_i (
  64                         .CIN(C[i]),
  65                         .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
  66                         .A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1),
  67                         .S0(Y[i]), .S1(Y1[i]),
  68                         .COUT(FCO[i])
  69                 );
  70
  71                 assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
  72                 if (i+1 < Y_WIDTH) begin
  73                         assign CO[i+1] = FCO[i];
  74                         assign Y[i+1] = Y1[i];
  75                 end
  76         end endgenerate
  77
  78         assign X = AA ^ BB;
  79 endmodule