Merge pull request #1559 from YosysHQ/efinix_test_fix
[yosys.git] / techlibs / ecp5 / brams_connect.py
1 #!/usr/bin/env python3
2
3 def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
4 ada_conn = [".ADA%d(%s)" % (i, ada_bits[i]) for i in range(len(ada_bits))]
5 adb_conn = [".ADB%d(%s)" % (i, adb_bits[i]) for i in range(len(adb_bits))]
6 dia_conn = [".DIA%d(%s)" % (i, dia_bits[i]) for i in range(len(dia_bits))]
7 dob_conn = [".DOB%d(%s)" % (i, dob_bits[i]) for i in range(len(dob_bits))]
8 print(" %s," % ", ".join(ada_conn), file=f)
9 print(" %s," % ", ".join(adb_conn), file=f)
10 print(" %s," % ", ".join(dia_conn), file=f)
11 print(" %s," % ", ".join(dob_conn), file=f)
12
13 def write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits):
14 adw_conn = [".ADW%d(%s)" % (i, adw_bits[i]) for i in range(len(adw_bits))]
15 adr_conn = [".ADR%d(%s)" % (i, adr_bits[i]) for i in range(len(adr_bits))]
16 di_conn = [".DI%d(%s)" % (i, di_bits[i]) for i in range(len(di_bits))]
17 do_conn = [".DO%d(%s)" % (i, do_bits[i]) for i in range(len(do_bits))]
18 be_conn = [".BE%d(%s)" % (i, be_bits[i]) for i in range(len(be_bits))]
19 print(" %s," % ", ".join(adw_conn), file=f)
20 print(" %s," % ", ".join(adr_conn), file=f)
21 print(" %s," % ", ".join(di_conn), file=f)
22 print(" %s," % ", ".join(do_conn), file=f)
23 print(" %s," % ", ".join(be_conn), file=f)
24
25 with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
26 ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
27 adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
28 dia_bits = ["A1DATA[0]"] + ["1'b0" for i in range(17)]
29 dob_bits = ["B1DATA[0]"]
30 write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
31
32 with open("techlibs/ecp5/bram_conn_2.vh", "w") as f:
33 ada_bits = ["1'b0"] + ["A1ADDR[%d]" % i for i in range(13)]
34 adb_bits = ["1'b0"] + ["B1ADDR[%d]" % i for i in range(13)]
35 dia_bits = ["A1DATA[%d]" % i for i in range(2)] + ["1'b0" for i in range(16)]
36 dob_bits = ["B1DATA[%d]" % i for i in range(2)]
37 write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
38
39 with open("techlibs/ecp5/bram_conn_4.vh", "w") as f:
40 ada_bits = ["1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(12)]
41 adb_bits = ["1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(12)]
42 dia_bits = ["A1DATA[%d]" % i for i in range(4)] + ["1'b0" for i in range(14)]
43 dob_bits = ["B1DATA[%d]" % i for i in range(4)]
44 write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
45
46 with open("techlibs/ecp5/bram_conn_9.vh", "w") as f:
47 ada_bits = ["1'b0", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(11)]
48 adb_bits = ["1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(11)]
49 dia_bits = ["A1DATA[%d]" % i for i in range(9)] + ["1'b0" for i in range(9)]
50 dob_bits = ["B1DATA[%d]" % i for i in range(9)]
51 write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
52
53 with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
54 ada_bits = ["A1EN[0]", "A1EN[1]", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(10)]
55 adb_bits = ["1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(10)]
56 dia_bits = ["A1DATA[%d]" % i for i in range(18)]
57 dob_bits = ["B1DATA[%d]" % i for i in range(18)]
58 write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
59
60 with open("techlibs/ecp5/bram_conn_36.vh", "w") as f:
61 adw_bits = ["A1ADDR[%d]" % i for i in range(9)]
62 adr_bits = ["1'b0", "1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(9)]
63 di_bits = ["A1DATA[%d]" % i for i in range(36)]
64 do_bits = ["B1DATA[%d]" % (i + 18) for i in range(18)] + ["B1DATA[%d]" % i for i in range(18)]
65 be_bits = ["A1EN[%d]" % i for i in range(4)]
66 write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits)