1 module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
2 parameter CFG_ABITS = 10;
3 parameter CFG_DBITS = 18;
4 parameter CFG_ENABLE_A = 2;
8 parameter [18431:0] INIT = 18432'bx;
14 input [CFG_ABITS-1:0] A1ADDR;
15 input [CFG_DBITS-1:0] A1DATA;
16 input [CFG_ENABLE_A-1:0] A1EN;
18 input [CFG_ABITS-1:0] B1ADDR;
19 output [CFG_DBITS-1:0] B1DATA;
22 localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
23 localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
25 localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
27 generate if (CFG_DBITS == 1) begin
29 `include "bram_init_1_2_4.vh"
34 .WRITEMODE_A(WRITEMODE_A),
35 .WRITEMODE_B("READBEFOREWRITE"),
38 `include "bram_conn_1.vh"
39 .CLKA(CLK2), .CLKB(CLK3),
40 .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
41 .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
42 .RSTA(1'b0), .RSTB(1'b0)
44 end else if (CFG_DBITS == 2) begin
46 `include "bram_init_1_2_4.vh"
51 .WRITEMODE_A(WRITEMODE_A),
52 .WRITEMODE_B("READBEFOREWRITE"),
55 `include "bram_conn_2.vh"
56 .CLKA(CLK2), .CLKB(CLK3),
57 .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
58 .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
59 .RSTA(1'b0), .RSTB(1'b0)
61 end else if (CFG_DBITS <= 4) begin
63 `include "bram_init_1_2_4.vh"
68 .WRITEMODE_A(WRITEMODE_A),
69 .WRITEMODE_B("READBEFOREWRITE"),
72 `include "bram_conn_4.vh"
73 .CLKA(CLK2), .CLKB(CLK3),
74 .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
75 .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
76 .RSTA(1'b0), .RSTB(1'b0)
78 end else if (CFG_DBITS <= 9) begin
80 `include "bram_init_9_18_36.vh"
85 .WRITEMODE_A(WRITEMODE_A),
86 .WRITEMODE_B("READBEFOREWRITE"),
89 `include "bram_conn_9.vh"
90 .CLKA(CLK2), .CLKB(CLK3),
91 .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
92 .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
93 .RSTA(1'b0), .RSTB(1'b0)
95 end else if (CFG_DBITS <= 18) begin
97 `include "bram_init_9_18_36.vh"
102 .WRITEMODE_A(WRITEMODE_A),
103 .WRITEMODE_B("READBEFOREWRITE"),
105 ) _TECHMAP_REPLACE_ (
106 `include "bram_conn_18.vh"
107 .CLKA(CLK2), .CLKB(CLK3),
108 .WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
109 .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
110 .RSTA(1'b0), .RSTB(1'b0)
113 wire TECHMAP_FAIL = 1'b1;
117 module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
118 parameter CFG_ABITS = 9;
119 parameter CFG_DBITS = 36;
120 parameter CFG_ENABLE_A = 4;
122 parameter CLKPOL2 = 1;
123 parameter CLKPOL3 = 1;
124 parameter [18431:0] INIT = 18432'bx;
129 input [CFG_ABITS-1:0] A1ADDR;
130 input [CFG_DBITS-1:0] A1DATA;
131 input [CFG_ENABLE_A-1:0] A1EN;
133 input [CFG_ABITS-1:0] B1ADDR;
134 output [CFG_DBITS-1:0] B1DATA;
137 localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
138 localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
140 localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
143 `include "bram_init_9_18_36.vh"
149 ) _TECHMAP_REPLACE_ (
150 `include "bram_conn_36.vh"
151 .CLKW(CLK2), .CLKR(CLK3),
153 .CER(B1EN), .OCER(1'b1),