techlibs/ecp5/cells_sim.v

   1 // ---------------------------------------
   2
   3 (* lib_whitebox *)
   4 module LUT4(input A, B, C, D, output Z);
   5     parameter [15:0] INIT = 16'h0000;
   6     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
   7     wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
   8     wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
   9     assign Z =      A ?          s1[1] :         s1[0];
  10 endmodule
  11
  12 // ---------------------------------------
  13 (* abc9_box_id=4, lib_whitebox *)
  14 module L6MUX21 (input D0, D1, SD, output Z);
  15         assign Z = SD ? D1 : D0;
  16 endmodule
  17
  18 // ---------------------------------------
  19 (* abc9_box_id=1, lib_whitebox *)
  20 module CCU2C(
  21         (* abc9_carry *)
  22         input  CIN,
  23         input  A0, B0, C0, D0, A1, B1, C1, D1,
  24         output S0, S1,
  25         (* abc9_carry *)
  26         output COUT
  27 );
  28         parameter [15:0] INIT0 = 16'h0000;
  29         parameter [15:0] INIT1 = 16'h0000;
  30         parameter INJECT1_0 = "YES";
  31         parameter INJECT1_1 = "YES";
  32
  33         // First half
  34         wire LUT4_0, LUT2_0;
  35         LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
  36         LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
  37         wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
  38         assign S0 = LUT4_0 ^ gated_cin_0;
  39
  40         wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
  41         wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
  42
  43         // Second half
  44         wire LUT4_1, LUT2_1;
  45         LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
  46         LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
  47         wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
  48         assign S1 = LUT4_1 ^ gated_cin_1;
  49
  50         wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
  51         assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
  52
  53 endmodule
  54
  55 // ---------------------------------------
  56
  57 module TRELLIS_RAM16X2 (
  58         input DI0, DI1,
  59         input WAD0, WAD1, WAD2, WAD3,
  60         input WRE, WCK,
  61         input RAD0, RAD1, RAD2, RAD3,
  62         output DO0, DO1
  63 );
  64         parameter WCKMUX = "WCK";
  65         parameter WREMUX = "WRE";
  66         parameter INITVAL_0 = 16'h0000;
  67         parameter INITVAL_1 = 16'h0000;
  68
  69         reg [1:0] mem[15:0];
  70
  71         integer i;
  72         initial begin
  73                 for (i = 0; i < 16; i = i + 1)
  74                         mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
  75         end
  76
  77         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
  78
  79         reg muxwre;
  80         always @(*)
  81                 case (WREMUX)
  82                         "1": muxwre = 1'b1;
  83                         "0": muxwre = 1'b0;
  84                         "INV": muxwre = ~WRE;
  85                         default: muxwre = WRE;
  86                 endcase
  87
  88
  89         always @(posedge muxwck)
  90                 if (muxwre)
  91                         mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
  92
  93         assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
  94 endmodule
  95
  96 // ---------------------------------------
  97 (* abc9_box_id=3, lib_whitebox *)
  98 module PFUMX (input ALUT, BLUT, C0, output Z);
  99         assign Z = C0 ? ALUT : BLUT;
 100 endmodule
 101
 102 // ---------------------------------------
 103 module TRELLIS_DPR16X4 (
 104         input  [3:0] DI,
 105         input  [3:0] WAD,
 106         input        WRE,
 107         input        WCK,
 108         input  [3:0] RAD,
 109         /* (* abc9_arrival=<TODO> *) */
 110         output [3:0] DO
 111 );
 112         parameter WCKMUX = "WCK";
 113         parameter WREMUX = "WRE";
 114         parameter [63:0] INITVAL = 64'h0000000000000000;
 115
 116         reg [3:0] mem[15:0];
 117
 118         integer i;
 119         initial begin
 120                 for (i = 0; i < 16; i = i + 1)
 121                         mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
 122         end
 123
 124         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 125
 126         reg muxwre;
 127         always @(*)
 128                 case (WREMUX)
 129                         "1": muxwre = 1'b1;
 130                         "0": muxwre = 1'b0;
 131                         "INV": muxwre = ~WRE;
 132                         default: muxwre = WRE;
 133                 endcase
 134
 135         always @(posedge muxwck)
 136                 if (muxwre)
 137                         mem[WAD] <= DI;
 138
 139         assign DO = mem[RAD];
 140 endmodule
 141
 142 // ---------------------------------------
 143
 144 module DPR16X4C (
 145                 input [3:0] DI,
 146                 input WCK, WRE,
 147                 input [3:0] RAD,
 148                 input [3:0] WAD,
 149                 output [3:0] DO
 150 );
 151         // For legacy Lattice compatibility, INITIVAL is a hex
 152         // string rather than a numeric parameter
 153         parameter INITVAL = "0x0000000000000000";
 154
 155         function [63:0] convert_initval;
 156                 input [143:0] hex_initval;
 157                 reg done;
 158                 reg [63:0] temp;
 159                 reg [7:0] char;
 160                 integer i;
 161                 begin
 162                         done = 1'b0;
 163                         temp = 0;
 164                         for (i = 0; i < 16; i = i + 1) begin
 165                                 if (!done) begin
 166                                         char = hex_initval[8*i +: 8];
 167                                         if (char == "x") begin
 168                                                 done = 1'b1;
 169                                         end else begin
 170                                                 if (char >= "0" && char <= "9")
 171                                                         temp[4*i +: 4] = char - "0";
 172                                                 else if (char >= "A" && char <= "F")
 173                                                         temp[4*i +: 4] = 10 + char - "A";
 174                                                 else if (char >= "a" && char <= "f")
 175                                                         temp[4*i +: 4] = 10 + char - "a";
 176                                         end
 177                                 end
 178                         end
 179                         convert_initval = temp;
 180                 end
 181         endfunction
 182
 183         localparam conv_initval = convert_initval(INITVAL);
 184
 185         reg [3:0] ram[0:15];
 186         integer i;
 187         initial begin
 188                 for (i = 0; i < 15; i = i + 1) begin
 189                         ram[i] <= conv_initval[4*i +: 4];
 190                 end
 191         end
 192
 193         always @(posedge WCK)
 194                 if (WRE)
 195                         ram[WAD] <= DI;
 196
 197         assign DO = ram[RAD];
 198
 199 endmodule
 200
 201 // ---------------------------------------
 202
 203 (* lib_whitebox *)
 204 module LUT2(input A, B, output Z);
 205     parameter [3:0] INIT = 4'h0;
 206     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
 207     assign Z =      A ?          s1[1] :         s1[0];
 208 endmodule
 209
 210 // ---------------------------------------
 211
 212 module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 213         parameter GSR = "ENABLED";
 214         parameter [127:0] CEMUX = "1";
 215         parameter CLKMUX = "CLK";
 216         parameter LSRMUX = "LSR";
 217         parameter SRMODE = "LSR_OVER_CE";
 218         parameter REGSET = "RESET";
 219         parameter [127:0] LSRMODE = "LSR";
 220
 221         wire muxce;
 222         generate
 223                 case (CEMUX)
 224                         "1": assign muxce = 1'b1;
 225                         "0": assign muxce = 1'b0;
 226                         "INV": assign muxce = ~CE;
 227                         default: assign muxce = CE;
 228                 endcase
 229         endgenerate
 230
 231         wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 232         wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 233         wire srval;
 234         generate
 235                 if (LSRMODE == "PRLD")
 236                         assign srval = M;
 237                 else
 238                         assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 239         endgenerate
 240
 241         initial Q = srval;
 242
 243         generate
 244                 if (SRMODE == "ASYNC") begin
 245                         always @(posedge muxclk, posedge muxlsr)
 246                                 if (muxlsr)
 247                                         Q <= srval;
 248                                 else if (muxce)
 249                                         Q <= DI;
 250                 end else begin
 251                         always @(posedge muxclk)
 252                                 if (muxlsr)
 253                                         Q <= srval;
 254                                 else if (muxce)
 255                                         Q <= DI;
 256                 end
 257         endgenerate
 258 endmodule
 259
 260 // ---------------------------------------
 261 (* keep *)
 262 module TRELLIS_IO(
 263         inout B,
 264         input I,
 265         input T,
 266         output O
 267 );
 268         parameter DIR = "INPUT";
 269         reg T_pd;
 270         always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 271
 272         generate
 273                 if (DIR == "INPUT") begin
 274                         assign B = 1'bz;
 275                         assign O = B;
 276                 end else if (DIR == "OUTPUT") begin
 277                         assign B = T_pd ? 1'bz : I;
 278                         assign O = 1'bx;
 279                 end else if (DIR == "BIDIR") begin
 280                         assign B = T_pd ? 1'bz : I;
 281                         assign O = B;
 282                 end else begin
 283                         ERROR_UNKNOWN_IO_MODE error();
 284                 end
 285         endgenerate
 286
 287 endmodule
 288
 289 // ---------------------------------------
 290
 291 module INV(input A, output Z);
 292         assign Z = !A;
 293 endmodule
 294
 295 // ---------------------------------------
 296
 297 module TRELLIS_SLICE(
 298         input A0, B0, C0, D0,
 299         input A1, B1, C1, D1,
 300         input M0, M1,
 301         input FCI, FXA, FXB,
 302
 303         input CLK, LSR, CE,
 304         input DI0, DI1,
 305
 306         input WD0, WD1,
 307         input WAD0, WAD1, WAD2, WAD3,
 308         input WRE, WCK,
 309
 310         output F0, Q0,
 311         output F1, Q1,
 312         output FCO, OFX0, OFX1,
 313
 314         output WDO0, WDO1, WDO2, WDO3,
 315         output WADO0, WADO1, WADO2, WADO3
 316 );
 317
 318         parameter MODE = "LOGIC";
 319         parameter GSR = "ENABLED";
 320         parameter SRMODE = "LSR_OVER_CE";
 321         parameter [127:0] CEMUX = "1";
 322         parameter CLKMUX = "CLK";
 323         parameter LSRMUX = "LSR";
 324         parameter LUT0_INITVAL = 16'h0000;
 325         parameter LUT1_INITVAL = 16'h0000;
 326         parameter REG0_SD = "0";
 327         parameter REG1_SD = "0";
 328         parameter REG0_REGSET = "RESET";
 329         parameter REG1_REGSET = "RESET";
 330         parameter REG0_LSRMODE = "LSR";
 331         parameter REG1_LSRMODE = "LSR";
 332         parameter [127:0] CCU2_INJECT1_0 = "NO";
 333         parameter [127:0] CCU2_INJECT1_1 = "NO";
 334         parameter WREMUX = "WRE";
 335         parameter WCKMUX = "WCK";
 336
 337         parameter A0MUX = "A0";
 338         parameter A1MUX = "A1";
 339         parameter B0MUX = "B0";
 340         parameter B1MUX = "B1";
 341         parameter C0MUX = "C0";
 342         parameter C1MUX = "C1";
 343         parameter D0MUX = "D0";
 344         parameter D1MUX = "D1";
 345
 346         wire A0m, B0m, C0m, D0m;
 347         wire A1m, B1m, C1m, D1m;
 348
 349         generate
 350                 if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
 351                 if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
 352                 if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
 353                 if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
 354                 if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
 355                 if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
 356                 if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
 357                 if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
 358
 359         endgenerate
 360
 361         function [15:0] permute_initval;
 362                 input [15:0] initval;
 363                 integer i;
 364                 begin
 365                         for (i = 0; i < 16; i = i + 1) begin
 366                                 permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
 367                         end
 368                 end
 369         endfunction
 370
 371         generate
 372                 if (MODE == "LOGIC") begin
 373                         // LUTs
 374                         LUT4 #(
 375                                 .INIT(LUT0_INITVAL)
 376                         ) lut4_0 (
 377                                 .A(A0m), .B(B0m), .C(C0m), .D(D0m),
 378                                 .Z(F0)
 379                         );
 380                         LUT4 #(
 381                                 .INIT(LUT1_INITVAL)
 382                         ) lut4_1 (
 383                                 .A(A1m), .B(B1m), .C(C1m), .D(D1m),
 384                                 .Z(F1)
 385                         );
 386                         // LUT expansion muxes
 387                         PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
 388                         L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
 389                 end else if (MODE == "CCU2") begin
 390                         CCU2C #(
 391                                 .INIT0(LUT0_INITVAL),
 392                                 .INIT1(LUT1_INITVAL),
 393                                 .INJECT1_0(CCU2_INJECT1_0),
 394                                 .INJECT1_1(CCU2_INJECT1_1)
 395                   ) ccu2c_i (
 396                                 .CIN(FCI),
 397                                 .A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
 398                                 .A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
 399                                 .S0(F0), .S1(F1),
 400                                 .COUT(FCO)
 401                         );
 402                 end else if (MODE == "RAMW") begin
 403                         assign WDO0 = C1m;
 404                         assign WDO1 = A1m;
 405                         assign WDO2 = D1m;
 406                         assign WDO3 = B1m;
 407                         assign WADO0 = D0m;
 408                         assign WADO1 = B0m;
 409                         assign WADO2 = C0m;
 410                         assign WADO3 = A0m;
 411                 end else if (MODE == "DPRAM") begin
 412                         TRELLIS_RAM16X2 #(
 413                                 .INITVAL_0(permute_initval(LUT0_INITVAL)),
 414                                 .INITVAL_1(permute_initval(LUT1_INITVAL)),
 415                                 .WREMUX(WREMUX)
 416                         ) ram_i (
 417                                 .DI0(WD0), .DI1(WD1),
 418                                 .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
 419                                 .WRE(WRE), .WCK(WCK),
 420                                 .RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
 421                                 .DO0(F0), .DO1(F1)
 422                         );
 423                         // TODO: confirm RAD and INITVAL ordering
 424                         // DPRAM mode contract?
 425 `ifdef FORMAL
 426                         always @(*) begin
 427                                 assert(A0m==A1m);
 428                                 assert(B0m==B1m);
 429                                 assert(C0m==C1m);
 430                                 assert(D0m==D1m);
 431                         end
 432 `endif
 433                 end else begin
 434                         ERROR_UNKNOWN_SLICE_MODE error();
 435                 end
 436         endgenerate
 437
 438         // FF input selection muxes
 439         wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
 440         wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
 441         // Flipflops
 442         TRELLIS_FF #(
 443                 .GSR(GSR),
 444                 .CEMUX(CEMUX),
 445                 .CLKMUX(CLKMUX),
 446                 .LSRMUX(LSRMUX),
 447                 .SRMODE(SRMODE),
 448                 .REGSET(REG0_REGSET),
 449                 .LSRMODE(REG0_LSRMODE)
 450         ) ff_0 (
 451                 .CLK(CLK), .LSR(LSR), .CE(CE),
 452                 .DI(muxdi0), .M(M0),
 453                 .Q(Q0)
 454         );
 455         TRELLIS_FF #(
 456                 .GSR(GSR),
 457                 .CEMUX(CEMUX),
 458                 .CLKMUX(CLKMUX),
 459                 .LSRMUX(LSRMUX),
 460                 .SRMODE(SRMODE),
 461                 .REGSET(REG1_REGSET),
 462                 .LSRMODE(REG1_LSRMODE)
 463         ) ff_1 (
 464                 .CLK(CLK), .LSR(LSR), .CE(CE),
 465                 .DI(muxdi1), .M(M1),
 466                 .Q(Q1)
 467         );
 468 endmodule
 469
 470 (* blackbox *)
 471 module DP16KD(
 472   input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
 473   input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
 474   input CEA, OCEA, CLKA, WEA, RSTA,
 475   input CSA2, CSA1, CSA0,
 476   output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
 477
 478   input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
 479   input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
 480   input CEB, OCEB, CLKB, WEB, RSTB,
 481   input CSB2, CSB1, CSB0,
 482   output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 483 );
 484         parameter DATA_WIDTH_A = 18;
 485         parameter DATA_WIDTH_B = 18;
 486
 487         parameter REGMODE_A = "NOREG";
 488         parameter REGMODE_B = "NOREG";
 489
 490         parameter RESETMODE = "SYNC";
 491         parameter ASYNC_RESET_RELEASE = "SYNC";
 492
 493         parameter CSDECODE_A = "0b000";
 494         parameter CSDECODE_B = "0b000";
 495
 496         parameter WRITEMODE_A = "NORMAL";
 497         parameter WRITEMODE_B = "NORMAL";
 498
 499         parameter DIA17MUX = "DIA17";
 500         parameter DIA16MUX = "DIA16";
 501         parameter DIA15MUX = "DIA15";
 502         parameter DIA14MUX = "DIA14";
 503         parameter DIA13MUX = "DIA13";
 504         parameter DIA12MUX = "DIA12";
 505         parameter DIA11MUX = "DIA11";
 506         parameter DIA10MUX = "DIA10";
 507         parameter DIA9MUX = "DIA9";
 508         parameter DIA8MUX = "DIA8";
 509         parameter DIA7MUX = "DIA7";
 510         parameter DIA6MUX = "DIA6";
 511         parameter DIA5MUX = "DIA5";
 512         parameter DIA4MUX = "DIA4";
 513         parameter DIA3MUX = "DIA3";
 514         parameter DIA2MUX = "DIA2";
 515         parameter DIA1MUX = "DIA1";
 516         parameter DIA0MUX = "DIA0";
 517         parameter ADA13MUX = "ADA13";
 518         parameter ADA12MUX = "ADA12";
 519         parameter ADA11MUX = "ADA11";
 520         parameter ADA10MUX = "ADA10";
 521         parameter ADA9MUX = "ADA9";
 522         parameter ADA8MUX = "ADA8";
 523         parameter ADA7MUX = "ADA7";
 524         parameter ADA6MUX = "ADA6";
 525         parameter ADA5MUX = "ADA5";
 526         parameter ADA4MUX = "ADA4";
 527         parameter ADA3MUX = "ADA3";
 528         parameter ADA2MUX = "ADA2";
 529         parameter ADA1MUX = "ADA1";
 530         parameter ADA0MUX = "ADA0";
 531         parameter CEAMUX = "CEA";
 532         parameter OCEAMUX = "OCEA";
 533         parameter CLKAMUX = "CLKA";
 534         parameter WEAMUX = "WEA";
 535         parameter RSTAMUX = "RSTA";
 536         parameter CSA2MUX = "CSA2";
 537         parameter CSA1MUX = "CSA1";
 538         parameter CSA0MUX = "CSA0";
 539         parameter DOA17MUX = "DOA17";
 540         parameter DOA16MUX = "DOA16";
 541         parameter DOA15MUX = "DOA15";
 542         parameter DOA14MUX = "DOA14";
 543         parameter DOA13MUX = "DOA13";
 544         parameter DOA12MUX = "DOA12";
 545         parameter DOA11MUX = "DOA11";
 546         parameter DOA10MUX = "DOA10";
 547         parameter DOA9MUX = "DOA9";
 548         parameter DOA8MUX = "DOA8";
 549         parameter DOA7MUX = "DOA7";
 550         parameter DOA6MUX = "DOA6";
 551         parameter DOA5MUX = "DOA5";
 552         parameter DOA4MUX = "DOA4";
 553         parameter DOA3MUX = "DOA3";
 554         parameter DOA2MUX = "DOA2";
 555         parameter DOA1MUX = "DOA1";
 556         parameter DOA0MUX = "DOA0";
 557         parameter DIB17MUX = "DIB17";
 558         parameter DIB16MUX = "DIB16";
 559         parameter DIB15MUX = "DIB15";
 560         parameter DIB14MUX = "DIB14";
 561         parameter DIB13MUX = "DIB13";
 562         parameter DIB12MUX = "DIB12";
 563         parameter DIB11MUX = "DIB11";
 564         parameter DIB10MUX = "DIB10";
 565         parameter DIB9MUX = "DIB9";
 566         parameter DIB8MUX = "DIB8";
 567         parameter DIB7MUX = "DIB7";
 568         parameter DIB6MUX = "DIB6";
 569         parameter DIB5MUX = "DIB5";
 570         parameter DIB4MUX = "DIB4";
 571         parameter DIB3MUX = "DIB3";
 572         parameter DIB2MUX = "DIB2";
 573         parameter DIB1MUX = "DIB1";
 574         parameter DIB0MUX = "DIB0";
 575         parameter ADB13MUX = "ADB13";
 576         parameter ADB12MUX = "ADB12";
 577         parameter ADB11MUX = "ADB11";
 578         parameter ADB10MUX = "ADB10";
 579         parameter ADB9MUX = "ADB9";
 580         parameter ADB8MUX = "ADB8";
 581         parameter ADB7MUX = "ADB7";
 582         parameter ADB6MUX = "ADB6";
 583         parameter ADB5MUX = "ADB5";
 584         parameter ADB4MUX = "ADB4";
 585         parameter ADB3MUX = "ADB3";
 586         parameter ADB2MUX = "ADB2";
 587         parameter ADB1MUX = "ADB1";
 588         parameter ADB0MUX = "ADB0";
 589         parameter CEBMUX = "CEB";
 590         parameter OCEBMUX = "OCEB";
 591         parameter CLKBMUX = "CLKB";
 592         parameter WEBMUX = "WEB";
 593         parameter RSTBMUX = "RSTB";
 594         parameter CSB2MUX = "CSB2";
 595         parameter CSB1MUX = "CSB1";
 596         parameter CSB0MUX = "CSB0";
 597         parameter DOB17MUX = "DOB17";
 598         parameter DOB16MUX = "DOB16";
 599         parameter DOB15MUX = "DOB15";
 600         parameter DOB14MUX = "DOB14";
 601         parameter DOB13MUX = "DOB13";
 602         parameter DOB12MUX = "DOB12";
 603         parameter DOB11MUX = "DOB11";
 604         parameter DOB10MUX = "DOB10";
 605         parameter DOB9MUX = "DOB9";
 606         parameter DOB8MUX = "DOB8";
 607         parameter DOB7MUX = "DOB7";
 608         parameter DOB6MUX = "DOB6";
 609         parameter DOB5MUX = "DOB5";
 610         parameter DOB4MUX = "DOB4";
 611         parameter DOB3MUX = "DOB3";
 612         parameter DOB2MUX = "DOB2";
 613         parameter DOB1MUX = "DOB1";
 614         parameter DOB0MUX = "DOB0";
 615
 616         parameter WID = 0;
 617
 618         parameter GSR = "ENABLED";
 619
 620         parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 621         parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 622         parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 623         parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 624         parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 625         parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 626         parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 627         parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 628         parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 629         parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 630         parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 631         parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 632         parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 633         parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 634         parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 635         parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 636         parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 637         parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 638         parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 639         parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 640         parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 641         parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 642         parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 643         parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 644         parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 645         parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 646         parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 647         parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 648         parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 649         parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 650         parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 651         parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 652         parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 653         parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 654         parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 655         parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 656         parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 657         parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 658         parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 659         parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 660         parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 661         parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 662         parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 663         parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 664         parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 665         parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 666         parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 667         parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 668         parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 669         parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 670         parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 671         parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 672         parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 673         parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 674         parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 675         parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 676         parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 677         parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 678         parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 679         parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 680         parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 681         parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 682         parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 683         parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 684 endmodule
 685
 686 `ifndef NO_INCLUDES
 687
 688 `include "cells_ff.vh"
 689 `include "cells_io.vh"
 690
 691 `endif