techlibs/ecp5/cells_sim.v

   1 // ---------------------------------------
   2
   3 (* abc9_lut=1, lib_whitebox *)
   4 module LUT4(input A, B, C, D, output Z);
   5     parameter [15:0] INIT = 16'h0000;
   6     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
   7     wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
   8     wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
   9     assign Z =      A ?          s1[1] :         s1[0];
  10     specify
  11         (A => Z) = 141;
  12         (B => Z) = 275;
  13         (C => Z) = 379;
  14         (D => Z) = 379;
  15     endspecify
  16 endmodule
  17
  18 // This is a placeholder for ABC9 to extract the area/delay
  19 //   cost of 5-input LUTs and is not intended to be instantiated
  20 // LUT5 = 2x LUT4 + PFUMX
  21 (* abc9_lut=2 *)
  22 module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
  23     specify
  24         (M0 => Z) = 151;
  25         (D => Z) = 239;
  26         (C => Z) = 373;
  27         (B => Z) = 477;
  28         (A => Z) = 477;
  29     endspecify
  30 endmodule
  31
  32 // This is a placeholder for ABC9 to extract the area/delay
  33 //   of 6-input LUTs and is not intended to be instantiated
  34 // LUT6 = 2x LUT5 + MUX2
  35 (* abc9_lut=4 *)
  36 module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
  37     specify
  38         (M1 => Z) = 148;
  39         (M0 => Z) = 292;
  40         (D => Z) = 380;
  41         (C => Z) = 514;
  42         (B => Z) = 618;
  43         (A => Z) = 618;
  44     endspecify
  45 endmodule
  46
  47 // This is a placeholder for ABC9 to extract the area/delay
  48 //   of 7-input LUTs and is not intended to be instantiated
  49 // LUT7 = 2x LUT6 + MUX2
  50 (* abc9_lut=8 *)
  51 module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
  52     specify
  53         (M2 => Z) = 148;
  54         (M1 => Z) = 289;
  55         (M0 => Z) = 433;
  56         (D => Z) = 521;
  57         (C => Z) = 655;
  58         (B => Z) = 759;
  59         (A => Z) = 759;
  60     endspecify
  61 endmodule
  62
  63 // ---------------------------------------
  64 (* abc9_box, lib_whitebox *)
  65 module L6MUX21 (input D0, D1, SD, output Z);
  66         assign Z = SD ? D1 : D0;
  67         specify
  68                 (D0 => Z) = 140;
  69                 (D1 => Z) = 141;
  70                 (SD => Z) = 148;
  71         endspecify
  72 endmodule
  73
  74 // ---------------------------------------
  75 (* abc9_box, lib_whitebox *)
  76 module CCU2C(
  77         (* abc9_carry *)
  78         input  CIN,
  79         input  A0, B0, C0, D0, A1, B1, C1, D1,
  80         output S0, S1,
  81         (* abc9_carry *)
  82         output COUT
  83 );
  84         parameter [15:0] INIT0 = 16'h0000;
  85         parameter [15:0] INIT1 = 16'h0000;
  86         parameter INJECT1_0 = "YES";
  87         parameter INJECT1_1 = "YES";
  88
  89         // First half
  90         wire LUT4_0, LUT2_0;
  91         LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
  92         LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
  93         wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
  94         assign S0 = LUT4_0 ^ gated_cin_0;
  95
  96         wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
  97         wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
  98
  99         // Second half
 100         wire LUT4_1, LUT2_1;
 101         LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
 102         LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
 103         wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 104         assign S1 = LUT4_1 ^ gated_cin_1;
 105
 106         wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
 107         assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
 108
 109         specify
 110                 (A0 => S0) = 379;
 111                 (B0 => S0) = 379;
 112                 (C0 => S0) = 275;
 113                 (D0 => S0) = 141;
 114                 (CIN => S0) = 257;
 115                 (A0 => S1) = 630;
 116                 (B0 => S1) = 630;
 117                 (C0 => S1) = 526;
 118                 (D0 => S1) = 392;
 119                 (A1 => S1) = 379;
 120                 (B1 => S1) = 379;
 121                 (C1 => S1) = 275;
 122                 (D1 => S1) = 141;
 123                 (CIN => S1) = 273;
 124                 (A0 => COUT) = 516;
 125                 (B0 => COUT) = 516;
 126                 (C0 => COUT) = 412;
 127                 (D0 => COUT) = 278;
 128                 (A1 => COUT) = 516;
 129                 (B1 => COUT) = 516;
 130                 (C1 => COUT) = 412;
 131                 (D1 => COUT) = 278;
 132                 (CIN => COUT) = 43;
 133         endspecify
 134 endmodule
 135
 136 // ---------------------------------------
 137
 138 module TRELLIS_RAM16X2 (
 139         input DI0, DI1,
 140         input WAD0, WAD1, WAD2, WAD3,
 141         input WRE, WCK,
 142         input RAD0, RAD1, RAD2, RAD3,
 143         output DO0, DO1
 144 );
 145         parameter WCKMUX = "WCK";
 146         parameter WREMUX = "WRE";
 147         parameter INITVAL_0 = 16'h0000;
 148         parameter INITVAL_1 = 16'h0000;
 149
 150         reg [1:0] mem[15:0];
 151
 152         integer i;
 153         initial begin
 154                 for (i = 0; i < 16; i = i + 1)
 155                         mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
 156         end
 157
 158         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 159
 160         reg muxwre;
 161         always @(*)
 162                 case (WREMUX)
 163                         "1": muxwre = 1'b1;
 164                         "0": muxwre = 1'b0;
 165                         "INV": muxwre = ~WRE;
 166                         default: muxwre = WRE;
 167                 endcase
 168
 169
 170         always @(posedge muxwck)
 171                 if (muxwre)
 172                         mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
 173
 174         assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
 175 endmodule
 176
 177 // ---------------------------------------
 178 (* abc9_box, lib_whitebox *)
 179 module PFUMX (input ALUT, BLUT, C0, output Z);
 180         assign Z = C0 ? ALUT : BLUT;
 181         specify
 182                 (ALUT => Z) = 98;
 183                 (BLUT => Z) = 98;
 184                 (C0 => Z) = 151;
 185         endspecify
 186 endmodule
 187
 188 // ---------------------------------------
 189 module TRELLIS_DPR16X4 (
 190         input  [3:0] DI,
 191         input  [3:0] WAD,
 192         input        WRE,
 193         input        WCK,
 194         input  [3:0] RAD,
 195         output [3:0] DO
 196 );
 197         parameter WCKMUX = "WCK";
 198         parameter WREMUX = "WRE";
 199         parameter [63:0] INITVAL = 64'h0000000000000000;
 200
 201         reg [3:0] mem[15:0];
 202
 203         integer i;
 204         initial begin
 205                 for (i = 0; i < 16; i = i + 1)
 206                         mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
 207         end
 208
 209         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 210
 211         reg muxwre;
 212         always @(*)
 213                 case (WREMUX)
 214                         "1": muxwre = 1'b1;
 215                         "0": muxwre = 1'b0;
 216                         "INV": muxwre = ~WRE;
 217                         default: muxwre = WRE;
 218                 endcase
 219
 220         always @(posedge muxwck)
 221                 if (muxwre)
 222                         mem[WAD] <= DI;
 223
 224         assign DO = mem[RAD];
 225 endmodule
 226
 227 // ---------------------------------------
 228
 229 module DPR16X4C (
 230                 input [3:0] DI,
 231                 input WCK, WRE,
 232                 input [3:0] RAD,
 233                 input [3:0] WAD,
 234                 output [3:0] DO
 235 );
 236         // For legacy Lattice compatibility, INITIVAL is a hex
 237         // string rather than a numeric parameter
 238         parameter INITVAL = "0x0000000000000000";
 239
 240         function [63:0] convert_initval;
 241                 input [143:0] hex_initval;
 242                 reg done;
 243                 reg [63:0] temp;
 244                 reg [7:0] char;
 245                 integer i;
 246                 begin
 247                         done = 1'b0;
 248                         temp = 0;
 249                         for (i = 0; i < 16; i = i + 1) begin
 250                                 if (!done) begin
 251                                         char = hex_initval[8*i +: 8];
 252                                         if (char == "x") begin
 253                                                 done = 1'b1;
 254                                         end else begin
 255                                                 if (char >= "0" && char <= "9")
 256                                                         temp[4*i +: 4] = char - "0";
 257                                                 else if (char >= "A" && char <= "F")
 258                                                         temp[4*i +: 4] = 10 + char - "A";
 259                                                 else if (char >= "a" && char <= "f")
 260                                                         temp[4*i +: 4] = 10 + char - "a";
 261                                         end
 262                                 end
 263                         end
 264                         convert_initval = temp;
 265                 end
 266         endfunction
 267
 268         localparam conv_initval = convert_initval(INITVAL);
 269
 270         reg [3:0] ram[0:15];
 271         integer i;
 272         initial begin
 273                 for (i = 0; i < 15; i = i + 1) begin
 274                         ram[i] <= conv_initval[4*i +: 4];
 275                 end
 276         end
 277
 278         always @(posedge WCK)
 279                 if (WRE)
 280                         ram[WAD] <= DI;
 281
 282         assign DO = ram[RAD];
 283
 284 endmodule
 285
 286 // ---------------------------------------
 287
 288 (* lib_whitebox *)
 289 module LUT2(input A, B, output Z);
 290     parameter [3:0] INIT = 4'h0;
 291     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
 292     assign Z =      A ?          s1[1] :         s1[0];
 293 endmodule
 294
 295 // ---------------------------------------
 296
 297 `ifdef YOSYS
 298 (* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *)
 299 `endif
 300 module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 301         parameter GSR = "ENABLED";
 302         parameter [127:0] CEMUX = "1";
 303         parameter CLKMUX = "CLK";
 304         parameter LSRMUX = "LSR";
 305         parameter SRMODE = "LSR_OVER_CE";
 306         parameter REGSET = "RESET";
 307         parameter [127:0] LSRMODE = "LSR";
 308
 309         wire muxce;
 310         generate
 311                 case (CEMUX)
 312                         "1": assign muxce = 1'b1;
 313                         "0": assign muxce = 1'b0;
 314                         "INV": assign muxce = ~CE;
 315                         default: assign muxce = CE;
 316                 endcase
 317         endgenerate
 318
 319         wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 320         wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 321         wire srval;
 322         generate
 323                 if (LSRMODE == "PRLD")
 324                         assign srval = M;
 325                 else
 326                         assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 327         endgenerate
 328
 329         initial Q = srval;
 330
 331         generate
 332                 if (SRMODE == "ASYNC") begin
 333                         always @(posedge muxclk, posedge muxlsr)
 334                                 if (muxlsr)
 335                                         Q <= srval;
 336                                 else if (muxce)
 337                                         Q <= DI;
 338                 end else begin
 339                         always @(posedge muxclk)
 340                                 if (muxlsr)
 341                                         Q <= srval;
 342                                 else if (muxce)
 343                                         Q <= DI;
 344                 end
 345         endgenerate
 346
 347         generate
 348                 // TODO
 349                 if (CLKMUX == "INV")
 350                         specify
 351                                 $setup(DI, negedge CLK, 0);
 352                                 $setup(CE, negedge CLK, 0);
 353                                 $setup(LSR, negedge CLK, 0);
 354                                 if (muxlsr) (negedge CLK => (Q : DI)) = 0;
 355                                 if (!muxlsr && muxce) (negedge CLK => (Q : srval)) = 0;
 356                         endspecify
 357                 else
 358                         specify
 359                                 $setup(DI, posedge CLK, 0);
 360                                 $setup(CE, posedge CLK, 0);
 361                                 $setup(LSR, posedge CLK, 0);
 362                                 if (muxlsr) (posedge CLK => (Q : srval)) = 0;
 363                                 if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0;
 364                         endspecify
 365         endgenerate
 366 endmodule
 367
 368 // ---------------------------------------
 369 (* keep *)
 370 module TRELLIS_IO(
 371         inout B,
 372         input I,
 373         input T,
 374         output O
 375 );
 376         parameter DIR = "INPUT";
 377         reg T_pd;
 378         always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 379
 380         generate
 381                 if (DIR == "INPUT") begin
 382                         assign B = 1'bz;
 383                         assign O = B;
 384                 end else if (DIR == "OUTPUT") begin
 385                         assign B = T_pd ? 1'bz : I;
 386                         assign O = 1'bx;
 387                 end else if (DIR == "BIDIR") begin
 388                         assign B = T_pd ? 1'bz : I;
 389                         assign O = B;
 390                 end else begin
 391                         ERROR_UNKNOWN_IO_MODE error();
 392                 end
 393         endgenerate
 394
 395 endmodule
 396
 397 // ---------------------------------------
 398
 399 module INV(input A, output Z);
 400         assign Z = !A;
 401 endmodule
 402
 403 // ---------------------------------------
 404
 405 module TRELLIS_SLICE(
 406         input A0, B0, C0, D0,
 407         input A1, B1, C1, D1,
 408         input M0, M1,
 409         input FCI, FXA, FXB,
 410
 411         input CLK, LSR, CE,
 412         input DI0, DI1,
 413
 414         input WD0, WD1,
 415         input WAD0, WAD1, WAD2, WAD3,
 416         input WRE, WCK,
 417
 418         output F0, Q0,
 419         output F1, Q1,
 420         output FCO, OFX0, OFX1,
 421
 422         output WDO0, WDO1, WDO2, WDO3,
 423         output WADO0, WADO1, WADO2, WADO3
 424 );
 425
 426         parameter MODE = "LOGIC";
 427         parameter GSR = "ENABLED";
 428         parameter SRMODE = "LSR_OVER_CE";
 429         parameter [127:0] CEMUX = "1";
 430         parameter CLKMUX = "CLK";
 431         parameter LSRMUX = "LSR";
 432         parameter LUT0_INITVAL = 16'h0000;
 433         parameter LUT1_INITVAL = 16'h0000;
 434         parameter REG0_SD = "0";
 435         parameter REG1_SD = "0";
 436         parameter REG0_REGSET = "RESET";
 437         parameter REG1_REGSET = "RESET";
 438         parameter REG0_LSRMODE = "LSR";
 439         parameter REG1_LSRMODE = "LSR";
 440         parameter [127:0] CCU2_INJECT1_0 = "NO";
 441         parameter [127:0] CCU2_INJECT1_1 = "NO";
 442         parameter WREMUX = "WRE";
 443         parameter WCKMUX = "WCK";
 444
 445         parameter A0MUX = "A0";
 446         parameter A1MUX = "A1";
 447         parameter B0MUX = "B0";
 448         parameter B1MUX = "B1";
 449         parameter C0MUX = "C0";
 450         parameter C1MUX = "C1";
 451         parameter D0MUX = "D0";
 452         parameter D1MUX = "D1";
 453
 454         wire A0m, B0m, C0m, D0m;
 455         wire A1m, B1m, C1m, D1m;
 456
 457         generate
 458                 if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
 459                 if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
 460                 if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
 461                 if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
 462                 if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
 463                 if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
 464                 if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
 465                 if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
 466
 467         endgenerate
 468
 469         function [15:0] permute_initval;
 470                 input [15:0] initval;
 471                 integer i;
 472                 begin
 473                         for (i = 0; i < 16; i = i + 1) begin
 474                                 permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
 475                         end
 476                 end
 477         endfunction
 478
 479         generate
 480                 if (MODE == "LOGIC") begin
 481                         // LUTs
 482                         LUT4 #(
 483                                 .INIT(LUT0_INITVAL)
 484                         ) lut4_0 (
 485                                 .A(A0m), .B(B0m), .C(C0m), .D(D0m),
 486                                 .Z(F0)
 487                         );
 488                         LUT4 #(
 489                                 .INIT(LUT1_INITVAL)
 490                         ) lut4_1 (
 491                                 .A(A1m), .B(B1m), .C(C1m), .D(D1m),
 492                                 .Z(F1)
 493                         );
 494                         // LUT expansion muxes
 495                         PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
 496                         L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
 497                 end else if (MODE == "CCU2") begin
 498                         CCU2C #(
 499                                 .INIT0(LUT0_INITVAL),
 500                                 .INIT1(LUT1_INITVAL),
 501                                 .INJECT1_0(CCU2_INJECT1_0),
 502                                 .INJECT1_1(CCU2_INJECT1_1)
 503                   ) ccu2c_i (
 504                                 .CIN(FCI),
 505                                 .A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
 506                                 .A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
 507                                 .S0(F0), .S1(F1),
 508                                 .COUT(FCO)
 509                         );
 510                 end else if (MODE == "RAMW") begin
 511                         assign WDO0 = C1m;
 512                         assign WDO1 = A1m;
 513                         assign WDO2 = D1m;
 514                         assign WDO3 = B1m;
 515                         assign WADO0 = D0m;
 516                         assign WADO1 = B0m;
 517                         assign WADO2 = C0m;
 518                         assign WADO3 = A0m;
 519                 end else if (MODE == "DPRAM") begin
 520                         TRELLIS_RAM16X2 #(
 521                                 .INITVAL_0(permute_initval(LUT0_INITVAL)),
 522                                 .INITVAL_1(permute_initval(LUT1_INITVAL)),
 523                                 .WREMUX(WREMUX)
 524                         ) ram_i (
 525                                 .DI0(WD0), .DI1(WD1),
 526                                 .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
 527                                 .WRE(WRE), .WCK(WCK),
 528                                 .RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
 529                                 .DO0(F0), .DO1(F1)
 530                         );
 531                         // TODO: confirm RAD and INITVAL ordering
 532                         // DPRAM mode contract?
 533 `ifdef FORMAL
 534                         always @(*) begin
 535                                 assert(A0m==A1m);
 536                                 assert(B0m==B1m);
 537                                 assert(C0m==C1m);
 538                                 assert(D0m==D1m);
 539                         end
 540 `endif
 541                 end else begin
 542                         ERROR_UNKNOWN_SLICE_MODE error();
 543                 end
 544         endgenerate
 545
 546         // FF input selection muxes
 547         wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
 548         wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
 549         // Flipflops
 550         TRELLIS_FF #(
 551                 .GSR(GSR),
 552                 .CEMUX(CEMUX),
 553                 .CLKMUX(CLKMUX),
 554                 .LSRMUX(LSRMUX),
 555                 .SRMODE(SRMODE),
 556                 .REGSET(REG0_REGSET),
 557                 .LSRMODE(REG0_LSRMODE)
 558         ) ff_0 (
 559                 .CLK(CLK), .LSR(LSR), .CE(CE),
 560                 .DI(muxdi0), .M(M0),
 561                 .Q(Q0)
 562         );
 563         TRELLIS_FF #(
 564                 .GSR(GSR),
 565                 .CEMUX(CEMUX),
 566                 .CLKMUX(CLKMUX),
 567                 .LSRMUX(LSRMUX),
 568                 .SRMODE(SRMODE),
 569                 .REGSET(REG1_REGSET),
 570                 .LSRMODE(REG1_LSRMODE)
 571         ) ff_1 (
 572                 .CLK(CLK), .LSR(LSR), .CE(CE),
 573                 .DI(muxdi1), .M(M1),
 574                 .Q(Q1)
 575         );
 576 endmodule
 577
 578 (* blackbox *)
 579 module DP16KD(
 580   input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
 581   input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
 582   input CEA, OCEA, CLKA, WEA, RSTA,
 583   input CSA2, CSA1, CSA0,
 584   output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
 585
 586   input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
 587   input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
 588   input CEB, OCEB, CLKB, WEB, RSTB,
 589   input CSB2, CSB1, CSB0,
 590   output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 591 );
 592         parameter DATA_WIDTH_A = 18;
 593         parameter DATA_WIDTH_B = 18;
 594
 595         parameter REGMODE_A = "NOREG";
 596         parameter REGMODE_B = "NOREG";
 597
 598         parameter RESETMODE = "SYNC";
 599         parameter ASYNC_RESET_RELEASE = "SYNC";
 600
 601         parameter CSDECODE_A = "0b000";
 602         parameter CSDECODE_B = "0b000";
 603
 604         parameter WRITEMODE_A = "NORMAL";
 605         parameter WRITEMODE_B = "NORMAL";
 606
 607         parameter DIA17MUX = "DIA17";
 608         parameter DIA16MUX = "DIA16";
 609         parameter DIA15MUX = "DIA15";
 610         parameter DIA14MUX = "DIA14";
 611         parameter DIA13MUX = "DIA13";
 612         parameter DIA12MUX = "DIA12";
 613         parameter DIA11MUX = "DIA11";
 614         parameter DIA10MUX = "DIA10";
 615         parameter DIA9MUX = "DIA9";
 616         parameter DIA8MUX = "DIA8";
 617         parameter DIA7MUX = "DIA7";
 618         parameter DIA6MUX = "DIA6";
 619         parameter DIA5MUX = "DIA5";
 620         parameter DIA4MUX = "DIA4";
 621         parameter DIA3MUX = "DIA3";
 622         parameter DIA2MUX = "DIA2";
 623         parameter DIA1MUX = "DIA1";
 624         parameter DIA0MUX = "DIA0";
 625         parameter ADA13MUX = "ADA13";
 626         parameter ADA12MUX = "ADA12";
 627         parameter ADA11MUX = "ADA11";
 628         parameter ADA10MUX = "ADA10";
 629         parameter ADA9MUX = "ADA9";
 630         parameter ADA8MUX = "ADA8";
 631         parameter ADA7MUX = "ADA7";
 632         parameter ADA6MUX = "ADA6";
 633         parameter ADA5MUX = "ADA5";
 634         parameter ADA4MUX = "ADA4";
 635         parameter ADA3MUX = "ADA3";
 636         parameter ADA2MUX = "ADA2";
 637         parameter ADA1MUX = "ADA1";
 638         parameter ADA0MUX = "ADA0";
 639         parameter CEAMUX = "CEA";
 640         parameter OCEAMUX = "OCEA";
 641         parameter CLKAMUX = "CLKA";
 642         parameter WEAMUX = "WEA";
 643         parameter RSTAMUX = "RSTA";
 644         parameter CSA2MUX = "CSA2";
 645         parameter CSA1MUX = "CSA1";
 646         parameter CSA0MUX = "CSA0";
 647         parameter DOA17MUX = "DOA17";
 648         parameter DOA16MUX = "DOA16";
 649         parameter DOA15MUX = "DOA15";
 650         parameter DOA14MUX = "DOA14";
 651         parameter DOA13MUX = "DOA13";
 652         parameter DOA12MUX = "DOA12";
 653         parameter DOA11MUX = "DOA11";
 654         parameter DOA10MUX = "DOA10";
 655         parameter DOA9MUX = "DOA9";
 656         parameter DOA8MUX = "DOA8";
 657         parameter DOA7MUX = "DOA7";
 658         parameter DOA6MUX = "DOA6";
 659         parameter DOA5MUX = "DOA5";
 660         parameter DOA4MUX = "DOA4";
 661         parameter DOA3MUX = "DOA3";
 662         parameter DOA2MUX = "DOA2";
 663         parameter DOA1MUX = "DOA1";
 664         parameter DOA0MUX = "DOA0";
 665         parameter DIB17MUX = "DIB17";
 666         parameter DIB16MUX = "DIB16";
 667         parameter DIB15MUX = "DIB15";
 668         parameter DIB14MUX = "DIB14";
 669         parameter DIB13MUX = "DIB13";
 670         parameter DIB12MUX = "DIB12";
 671         parameter DIB11MUX = "DIB11";
 672         parameter DIB10MUX = "DIB10";
 673         parameter DIB9MUX = "DIB9";
 674         parameter DIB8MUX = "DIB8";
 675         parameter DIB7MUX = "DIB7";
 676         parameter DIB6MUX = "DIB6";
 677         parameter DIB5MUX = "DIB5";
 678         parameter DIB4MUX = "DIB4";
 679         parameter DIB3MUX = "DIB3";
 680         parameter DIB2MUX = "DIB2";
 681         parameter DIB1MUX = "DIB1";
 682         parameter DIB0MUX = "DIB0";
 683         parameter ADB13MUX = "ADB13";
 684         parameter ADB12MUX = "ADB12";
 685         parameter ADB11MUX = "ADB11";
 686         parameter ADB10MUX = "ADB10";
 687         parameter ADB9MUX = "ADB9";
 688         parameter ADB8MUX = "ADB8";
 689         parameter ADB7MUX = "ADB7";
 690         parameter ADB6MUX = "ADB6";
 691         parameter ADB5MUX = "ADB5";
 692         parameter ADB4MUX = "ADB4";
 693         parameter ADB3MUX = "ADB3";
 694         parameter ADB2MUX = "ADB2";
 695         parameter ADB1MUX = "ADB1";
 696         parameter ADB0MUX = "ADB0";
 697         parameter CEBMUX = "CEB";
 698         parameter OCEBMUX = "OCEB";
 699         parameter CLKBMUX = "CLKB";
 700         parameter WEBMUX = "WEB";
 701         parameter RSTBMUX = "RSTB";
 702         parameter CSB2MUX = "CSB2";
 703         parameter CSB1MUX = "CSB1";
 704         parameter CSB0MUX = "CSB0";
 705         parameter DOB17MUX = "DOB17";
 706         parameter DOB16MUX = "DOB16";
 707         parameter DOB15MUX = "DOB15";
 708         parameter DOB14MUX = "DOB14";
 709         parameter DOB13MUX = "DOB13";
 710         parameter DOB12MUX = "DOB12";
 711         parameter DOB11MUX = "DOB11";
 712         parameter DOB10MUX = "DOB10";
 713         parameter DOB9MUX = "DOB9";
 714         parameter DOB8MUX = "DOB8";
 715         parameter DOB7MUX = "DOB7";
 716         parameter DOB6MUX = "DOB6";
 717         parameter DOB5MUX = "DOB5";
 718         parameter DOB4MUX = "DOB4";
 719         parameter DOB3MUX = "DOB3";
 720         parameter DOB2MUX = "DOB2";
 721         parameter DOB1MUX = "DOB1";
 722         parameter DOB0MUX = "DOB0";
 723
 724         parameter WID = 0;
 725
 726         parameter GSR = "ENABLED";
 727
 728         parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 729         parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 730         parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 731         parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 732         parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 733         parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 734         parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 735         parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 736         parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 737         parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 738         parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 739         parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 740         parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 741         parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 742         parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 743         parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 744         parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 745         parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 746         parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 747         parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 748         parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 749         parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 750         parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 751         parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 752         parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 753         parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 754         parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 755         parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 756         parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 757         parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 758         parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 759         parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 760         parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 761         parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 762         parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 763         parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 764         parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 765         parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 766         parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 767         parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 768         parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 769         parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 770         parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 771         parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 772         parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 773         parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 774         parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 775         parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 776         parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 777         parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 778         parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 779         parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 780         parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 781         parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 782         parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 783         parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 784         parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 785         parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 786         parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 787         parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 788         parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 789         parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 790         parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 791         parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 792 endmodule
 793
 794 `ifndef NO_INCLUDES
 795
 796 `include "cells_ff.vh"
 797 `include "cells_io.vh"
 798
 799 `endif