1 // ---------------------------------------
3 module LUT4(input A, B, C, D, output Z);
4 parameter [15:0] INIT = 16'h0000;
5 wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
6 wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
7 wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
8 assign Z = A ? s1[1] : s1[0];
11 // ---------------------------------------
12 (* abc_box_id=4, lib_whitebox *)
13 module L6MUX21 (input D0, D1, SD, output Z);
14 assign Z = SD ? D1 : D0;
17 // ---------------------------------------
18 (* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
19 module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
22 parameter [15:0] INIT0 = 16'h0000;
23 parameter [15:0] INIT1 = 16'h0000;
24 parameter INJECT1_0 = "YES";
25 parameter INJECT1_1 = "YES";
30 assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
31 assign LUT2_0 = INIT0[{2'b00, B0, A0}];
33 LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
34 LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
36 wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
37 assign S0 = LUT4_0 ^ gated_cin_0;
39 wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
40 wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
45 assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
46 assign LUT2_1 = INIT1[{2'b00, B1, A1}];
48 LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
49 LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
51 wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
52 assign S1 = LUT4_1 ^ gated_cin_1;
54 wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
55 assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
59 // ---------------------------------------
61 module TRELLIS_RAM16X2 (
63 input WAD0, WAD1, WAD2, WAD3,
65 input RAD0, RAD1, RAD2, RAD3,
68 parameter WCKMUX = "WCK";
69 parameter WREMUX = "WRE";
70 parameter INITVAL_0 = 16'h0000;
71 parameter INITVAL_1 = 16'h0000;
77 for (i = 0; i < 16; i = i + 1)
78 mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
81 wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
89 default: muxwre = WRE;
93 always @(posedge muxwck)
95 mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
97 assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
100 // ---------------------------------------
101 (* abc_box_id=3, lib_whitebox *)
102 module PFUMX (input ALUT, BLUT, C0, output Z);
103 assign Z = C0 ? ALUT : BLUT;
106 // ---------------------------------------
107 //(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
108 module TRELLIS_DPR16X4 (
115 parameter WCKMUX = "WCK";
116 parameter WREMUX = "WRE";
117 parameter [63:0] INITVAL = 64'h0000000000000000;
123 for (i = 0; i < 16; i = i + 1)
124 mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
127 wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
134 "INV": muxwre = ~WRE;
135 default: muxwre = WRE;
138 always @(posedge muxwck)
142 assign DO = mem[RAD];
145 // ---------------------------------------
154 // For legacy Lattice compatibility, INITIVAL is a hex
155 // string rather than a numeric parameter
156 parameter INITVAL = "0x0000000000000000";
158 function [63:0] convert_initval;
159 input [143:0] hex_initval;
167 for (i = 0; i < 16; i = i + 1) begin
169 char = hex_initval[8*i +: 8];
170 if (char == "x") begin
173 if (char >= "0" && char <= "9")
174 temp[4*i +: 4] = char - "0";
175 else if (char >= "A" && char <= "F")
176 temp[4*i +: 4] = 10 + char - "A";
177 else if (char >= "a" && char <= "f")
178 temp[4*i +: 4] = 10 + char - "a";
182 convert_initval = temp;
186 localparam conv_initval = convert_initval(INITVAL);
191 for (i = 0; i < 15; i = i + 1) begin
192 ram[i] <= conv_initval[4*i +: 4];
196 always @(posedge WCK)
200 assign DO = ram[RAD];
204 // ---------------------------------------
206 module LUT2(input A, B, output Z);
207 parameter [3:0] INIT = 4'h0;
208 wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
209 assign Z = A ? s1[1] : s1[0];
212 // ---------------------------------------
214 module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
215 parameter GSR = "ENABLED";
216 parameter [127:0] CEMUX = "1";
217 parameter CLKMUX = "CLK";
218 parameter LSRMUX = "LSR";
219 parameter SRMODE = "LSR_OVER_CE";
220 parameter REGSET = "RESET";
221 parameter [127:0] LSRMODE = "LSR";
232 wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
233 wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
236 if (LSRMODE == "PRLD")
239 assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
245 if (SRMODE == "ASYNC") begin
246 always @(posedge muxclk, posedge muxlsr)
252 always @(posedge muxclk)
261 // ---------------------------------------
269 parameter DIR = "INPUT";
271 always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
274 if (DIR == "INPUT") begin
277 end else if (DIR == "OUTPUT") begin
278 assign B = T_pd ? 1'bz : I;
280 end else if (DIR == "BIDIR") begin
281 assign B = T_pd ? 1'bz : I;
284 ERROR_UNKNOWN_IO_MODE error();
290 // ---------------------------------------
292 module INV(input A, output Z);
296 // ---------------------------------------
298 module TRELLIS_SLICE(
299 input A0, B0, C0, D0,
300 input A1, B1, C1, D1,
308 input WAD0, WAD1, WAD2, WAD3,
313 output FCO, OFX0, OFX1,
315 output WDO0, WDO1, WDO2, WDO3,
316 output WADO0, WADO1, WADO2, WADO3
319 parameter MODE = "LOGIC";
320 parameter GSR = "ENABLED";
321 parameter SRMODE = "LSR_OVER_CE";
322 parameter [127:0] CEMUX = "1";
323 parameter CLKMUX = "CLK";
324 parameter LSRMUX = "LSR";
325 parameter LUT0_INITVAL = 16'h0000;
326 parameter LUT1_INITVAL = 16'h0000;
327 parameter REG0_SD = "0";
328 parameter REG1_SD = "0";
329 parameter REG0_REGSET = "RESET";
330 parameter REG1_REGSET = "RESET";
331 parameter REG0_LSRMODE = "LSR";
332 parameter REG1_LSRMODE = "LSR";
333 parameter [127:0] CCU2_INJECT1_0 = "NO";
334 parameter [127:0] CCU2_INJECT1_1 = "NO";
335 parameter WREMUX = "WRE";
337 function [15:0] permute_initval;
338 input [15:0] initval;
341 for (i = 0; i < 16; i = i + 1) begin
342 permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
348 if (MODE == "LOGIC") begin
353 .A(A0), .B(B0), .C(C0), .D(D0),
359 .A(A1), .B(B1), .C(C1), .D(D1),
362 // LUT expansion muxes
363 PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
364 L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
365 end else if (MODE == "CCU2") begin
367 .INIT0(LUT0_INITVAL),
368 .INIT1(LUT1_INITVAL),
369 .INJECT1_0(CCU2_INJECT1_0),
370 .INJECT1_1(CCU2_INJECT1_1)
373 .A0(A0), .B0(B0), .C0(C0), .D0(D0),
374 .A1(A1), .B1(B1), .C1(C1), .D1(D1),
378 end else if (MODE == "RAMW") begin
387 end else if (MODE == "DPRAM") begin
389 .INITVAL_0(permute_initval(LUT0_INITVAL)),
390 .INITVAL_1(permute_initval(LUT1_INITVAL)),
393 .DI0(WD0), .DI1(WD1),
394 .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
395 .WRE(WRE), .WCK(WCK),
396 .RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
399 // TODO: confirm RAD and INITVAL ordering
400 // DPRAM mode contract?
408 ERROR_UNKNOWN_SLICE_MODE error();
412 // FF input selection muxes
413 wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
414 wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
422 .REGSET(REG0_REGSET),
423 .LSRMODE(REG0_LSRMODE)
425 .CLK(CLK), .LSR(LSR), .CE(CE),
435 .REGSET(REG1_REGSET),
436 .LSRMODE(REG1_LSRMODE)
438 .CLK(CLK), .LSR(LSR), .CE(CE),
446 input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
447 input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
448 input CEA, OCEA, CLKA, WEA, RSTA,
449 input CSA2, CSA1, CSA0,
450 output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
452 input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
453 input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
454 input CEB, OCEB, CLKB, WEB, RSTB,
455 input CSB2, CSB1, CSB0,
456 output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
458 parameter DATA_WIDTH_A = 18;
459 parameter DATA_WIDTH_B = 18;
461 parameter REGMODE_A = "NOREG";
462 parameter REGMODE_B = "NOREG";
464 parameter RESETMODE = "SYNC";
465 parameter ASYNC_RESET_RELEASE = "SYNC";
467 parameter CSDECODE_A = "0b000";
468 parameter CSDECODE_B = "0b000";
470 parameter WRITEMODE_A = "NORMAL";
471 parameter WRITEMODE_B = "NORMAL";
473 parameter CLKAMUX = "CLKA";
474 parameter CLKBMUX = "CLKB";
476 parameter GSR = "ENABLED";
478 parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
479 parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
480 parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
481 parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
482 parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
483 parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
484 parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
485 parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
486 parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
487 parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
488 parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
489 parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
490 parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
491 parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
492 parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
493 parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
494 parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
495 parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
496 parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
497 parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
498 parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
499 parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
500 parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
501 parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
502 parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
503 parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
504 parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
505 parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
506 parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
507 parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
508 parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
509 parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
510 parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
511 parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
512 parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
513 parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
514 parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
515 parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
516 parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
517 parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
518 parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
519 parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
520 parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
521 parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
522 parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
523 parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
524 parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
525 parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
526 parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
527 parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
528 parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
529 parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
530 parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
531 parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
532 parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
533 parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
534 parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
535 parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
536 parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
537 parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
538 parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
539 parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
540 parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
541 parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
544 // TODO: Diamond flip-flops
545 // module FD1P3AX(); endmodule
546 // module FD1P3AY(); endmodule
547 // module FD1P3BX(); endmodule
548 // module FD1P3DX(); endmodule
549 // module FD1P3IX(); endmodule
550 // module FD1P3JX(); endmodule
551 // module FD1S3AX(); endmodule
552 // module FD1S3AY(); endmodule
553 module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
554 module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
555 module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
556 module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
557 // module FL1P3AY(); endmodule
558 // module FL1P3AZ(); endmodule
559 // module FL1P3BX(); endmodule
560 // module FL1P3DX(); endmodule
561 // module FL1P3IY(); endmodule
562 // module FL1P3JY(); endmodule
563 // module FL1S3AX(); endmodule
564 // module FL1S3AY(); endmodule
566 // Diamond I/O buffers
567 module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
568 module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
569 module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
570 module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I)); endmodule
571 module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
572 module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
573 module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
574 module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
575 module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
576 module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
577 module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
578 module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) tio (.B(A), .O(Z)); endmodule
579 module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(Z), .I(A)); endmodule
581 // Diamond I/O registers
582 module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
583 module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
584 module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
585 module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
587 module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
588 module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
589 module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
590 module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
592 // TODO: Diamond I/O latches
593 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
594 // module IFS1S1D(input CD, D, SCLK, output Q); endmodule
595 // module IFS1S1I(input PD, D, SCLK, output Q); endmodule
596 // module IFS1S1J(input CD, D, SCLK, output Q); endmodule