techlibs/ecp5/cells_sim.v

   1 // ---------------------------------------
   2
   3 module LUT4(input A, B, C, D, output Z);
   4     parameter [15:0] INIT = 16'h0000;
   5     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
   6     wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
   7     wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
   8     assign Z =      A ?          s1[1] :         s1[0];
   9 endmodule
  10
  11 // ---------------------------------------
  12 (* abc_box_id=4, lib_whitebox *)
  13 module L6MUX21 (input D0, D1, SD, output Z);
  14         assign Z = SD ? D1 : D0;
  15 endmodule
  16
  17 // ---------------------------------------
  18 (* abc_box_id=1, lib_whitebox *)
  19 module CCU2C(
  20         (* abc_carry *)
  21         input  CIN,
  22         input  A0, B0, C0, D0, A1, B1, C1, D1,
  23         output S0, S1,
  24         (* abc_carry *)
  25         output COUT
  26 );
  27         parameter [15:0] INIT0 = 16'h0000;
  28         parameter [15:0] INIT1 = 16'h0000;
  29         parameter INJECT1_0 = "YES";
  30         parameter INJECT1_1 = "YES";
  31
  32         // First half
  33         wire LUT4_0, LUT2_0;
  34 `ifdef _ABC
  35         assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
  36         assign LUT2_0 = INIT0[{2'b00, B0, A0}];
  37 `else
  38         LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
  39         LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
  40 `endif
  41         wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
  42         assign S0 = LUT4_0 ^ gated_cin_0;
  43
  44         wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
  45         wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
  46
  47         // Second half
  48         wire LUT4_1, LUT2_1;
  49 `ifdef _ABC
  50         assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
  51         assign LUT2_1 = INIT1[{2'b00, B1, A1}];
  52 `else
  53         LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
  54         LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
  55 `endif
  56         wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
  57         assign S1 = LUT4_1 ^ gated_cin_1;
  58
  59         wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
  60         assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
  61
  62 endmodule
  63
  64 // ---------------------------------------
  65
  66 module TRELLIS_RAM16X2 (
  67         input DI0, DI1,
  68         input WAD0, WAD1, WAD2, WAD3,
  69         input WRE, WCK,
  70         input RAD0, RAD1, RAD2, RAD3,
  71         output DO0, DO1
  72 );
  73         parameter WCKMUX = "WCK";
  74         parameter WREMUX = "WRE";
  75         parameter INITVAL_0 = 16'h0000;
  76         parameter INITVAL_1 = 16'h0000;
  77
  78         reg [1:0] mem[15:0];
  79
  80         integer i;
  81         initial begin
  82                 for (i = 0; i < 16; i = i + 1)
  83                         mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
  84         end
  85
  86         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
  87
  88         reg muxwre;
  89         always @(*)
  90                 case (WREMUX)
  91                         "1": muxwre = 1'b1;
  92                         "0": muxwre = 1'b0;
  93                         "INV": muxwre = ~WRE;
  94                         default: muxwre = WRE;
  95                 endcase
  96
  97
  98         always @(posedge muxwck)
  99                 if (muxwre)
 100                         mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
 101
 102         assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
 103 endmodule
 104
 105 // ---------------------------------------
 106 (* abc_box_id=3, lib_whitebox *)
 107 module PFUMX (input ALUT, BLUT, C0, output Z);
 108         assign Z = C0 ? ALUT : BLUT;
 109 endmodule
 110
 111 // ---------------------------------------
 112 module TRELLIS_DPR16X4 (
 113         input  [3:0] DI,
 114         input  [3:0] WAD,
 115         input        WRE,
 116         input        WCK,
 117         input  [3:0] RAD,
 118         /* (* abc_arrival=<TODO> *) */
 119         output [3:0] DO
 120 );
 121         parameter WCKMUX = "WCK";
 122         parameter WREMUX = "WRE";
 123         parameter [63:0] INITVAL = 64'h0000000000000000;
 124
 125         reg [3:0] mem[15:0];
 126
 127         integer i;
 128         initial begin
 129                 for (i = 0; i < 16; i = i + 1)
 130                         mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
 131         end
 132
 133         wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 134
 135         reg muxwre;
 136         always @(*)
 137                 case (WREMUX)
 138                         "1": muxwre = 1'b1;
 139                         "0": muxwre = 1'b0;
 140                         "INV": muxwre = ~WRE;
 141                         default: muxwre = WRE;
 142                 endcase
 143
 144         always @(posedge muxwck)
 145                 if (muxwre)
 146                         mem[WAD] <= DI;
 147
 148         assign DO = mem[RAD];
 149 endmodule
 150
 151 // ---------------------------------------
 152
 153 module DPR16X4C (
 154                 input [3:0] DI,
 155                 input WCK, WRE,
 156                 input [3:0] RAD,
 157                 input [3:0] WAD,
 158                 output [3:0] DO
 159 );
 160         // For legacy Lattice compatibility, INITIVAL is a hex
 161         // string rather than a numeric parameter
 162         parameter INITVAL = "0x0000000000000000";
 163
 164         function [63:0] convert_initval;
 165                 input [143:0] hex_initval;
 166                 reg done;
 167                 reg [63:0] temp;
 168                 reg [7:0] char;
 169                 integer i;
 170                 begin
 171                         done = 1'b0;
 172                         temp = 0;
 173                         for (i = 0; i < 16; i = i + 1) begin
 174                                 if (!done) begin
 175                                         char = hex_initval[8*i +: 8];
 176                                         if (char == "x") begin
 177                                                 done = 1'b1;
 178                                         end else begin
 179                                                 if (char >= "0" && char <= "9")
 180                                                         temp[4*i +: 4] = char - "0";
 181                                                 else if (char >= "A" && char <= "F")
 182                                                         temp[4*i +: 4] = 10 + char - "A";
 183                                                 else if (char >= "a" && char <= "f")
 184                                                         temp[4*i +: 4] = 10 + char - "a";
 185                                         end
 186                                 end
 187                         end
 188                         convert_initval = temp;
 189                 end
 190         endfunction
 191
 192         localparam conv_initval = convert_initval(INITVAL);
 193
 194         reg [3:0] ram[0:15];
 195         integer i;
 196         initial begin
 197                 for (i = 0; i < 15; i = i + 1) begin
 198                         ram[i] <= conv_initval[4*i +: 4];
 199                 end
 200         end
 201
 202         always @(posedge WCK)
 203                 if (WRE)
 204                         ram[WAD] <= DI;
 205
 206         assign DO = ram[RAD];
 207
 208 endmodule
 209
 210 // ---------------------------------------
 211
 212 module LUT2(input A, B, output Z);
 213     parameter [3:0] INIT = 4'h0;
 214     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
 215     assign Z =      A ?          s1[1] :         s1[0];
 216 endmodule
 217
 218 // ---------------------------------------
 219
 220 module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 221         parameter GSR = "ENABLED";
 222         parameter [127:0] CEMUX = "1";
 223         parameter CLKMUX = "CLK";
 224         parameter LSRMUX = "LSR";
 225         parameter SRMODE = "LSR_OVER_CE";
 226         parameter REGSET = "RESET";
 227         parameter [127:0] LSRMODE = "LSR";
 228
 229         wire muxce;
 230         generate
 231                 case (CEMUX)
 232                         "1": assign muxce = 1'b1;
 233                         "0": assign muxce = 1'b0;
 234                         "INV": assign muxce = ~CE;
 235                         default: assign muxce = CE;
 236                 endcase
 237         endgenerate
 238
 239         wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 240         wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 241         wire srval;
 242         generate
 243                 if (LSRMODE == "PRLD")
 244                         assign srval = M;
 245                 else
 246                         assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 247         endgenerate
 248
 249         initial Q = srval;
 250
 251         generate
 252                 if (SRMODE == "ASYNC") begin
 253                         always @(posedge muxclk, posedge muxlsr)
 254                                 if (muxlsr)
 255                                         Q <= srval;
 256                                 else if (muxce)
 257                                         Q <= DI;
 258                 end else begin
 259                         always @(posedge muxclk)
 260                                 if (muxlsr)
 261                                         Q <= srval;
 262                                 else if (muxce)
 263                                         Q <= DI;
 264                 end
 265         endgenerate
 266 endmodule
 267
 268 // ---------------------------------------
 269 (* keep *)
 270 module TRELLIS_IO(
 271         inout B,
 272         input I,
 273         input T,
 274         output O
 275 );
 276         parameter DIR = "INPUT";
 277         reg T_pd;
 278         always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 279
 280         generate
 281                 if (DIR == "INPUT") begin
 282                         assign B = 1'bz;
 283                         assign O = B;
 284                 end else if (DIR == "OUTPUT") begin
 285                         assign B = T_pd ? 1'bz : I;
 286                         assign O = 1'bx;
 287                 end else if (DIR == "BIDIR") begin
 288                         assign B = T_pd ? 1'bz : I;
 289                         assign O = B;
 290                 end else begin
 291                         ERROR_UNKNOWN_IO_MODE error();
 292                 end
 293         endgenerate
 294
 295 endmodule
 296
 297 // ---------------------------------------
 298
 299 module INV(input A, output Z);
 300         assign Z = !A;
 301 endmodule
 302
 303 // ---------------------------------------
 304
 305 module TRELLIS_SLICE(
 306         input A0, B0, C0, D0,
 307         input A1, B1, C1, D1,
 308         input M0, M1,
 309         input FCI, FXA, FXB,
 310
 311         input CLK, LSR, CE,
 312         input DI0, DI1,
 313
 314         input WD0, WD1,
 315         input WAD0, WAD1, WAD2, WAD3,
 316         input WRE, WCK,
 317
 318         output F0, Q0,
 319         output F1, Q1,
 320         output FCO, OFX0, OFX1,
 321
 322         output WDO0, WDO1, WDO2, WDO3,
 323         output WADO0, WADO1, WADO2, WADO3
 324 );
 325
 326         parameter MODE = "LOGIC";
 327         parameter GSR = "ENABLED";
 328         parameter SRMODE = "LSR_OVER_CE";
 329         parameter [127:0] CEMUX = "1";
 330         parameter CLKMUX = "CLK";
 331         parameter LSRMUX = "LSR";
 332         parameter LUT0_INITVAL = 16'h0000;
 333         parameter LUT1_INITVAL = 16'h0000;
 334         parameter REG0_SD = "0";
 335         parameter REG1_SD = "0";
 336         parameter REG0_REGSET = "RESET";
 337         parameter REG1_REGSET = "RESET";
 338         parameter REG0_LSRMODE = "LSR";
 339         parameter REG1_LSRMODE = "LSR";
 340         parameter [127:0] CCU2_INJECT1_0 = "NO";
 341         parameter [127:0] CCU2_INJECT1_1 = "NO";
 342         parameter WREMUX = "WRE";
 343         parameter WCKMUX = "WCK";
 344
 345         parameter A0MUX = "A0";
 346         parameter A1MUX = "A1";
 347         parameter B0MUX = "B0";
 348         parameter B1MUX = "B1";
 349         parameter C0MUX = "C0";
 350         parameter C1MUX = "C1";
 351         parameter D0MUX = "D0";
 352         parameter D1MUX = "D1";
 353
 354         wire A0m, B0m, C0m, D0m;
 355         wire A1m, B1m, C1m, D1m;
 356
 357         generate
 358                 if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
 359                 if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
 360                 if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
 361                 if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
 362                 if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
 363                 if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
 364                 if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
 365                 if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
 366
 367         endgenerate
 368
 369         function [15:0] permute_initval;
 370                 input [15:0] initval;
 371                 integer i;
 372                 begin
 373                         for (i = 0; i < 16; i = i + 1) begin
 374                                 permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
 375                         end
 376                 end
 377         endfunction
 378
 379         generate
 380                 if (MODE == "LOGIC") begin
 381                         // LUTs
 382                         LUT4 #(
 383                                 .INIT(LUT0_INITVAL)
 384                         ) lut4_0 (
 385                                 .A(A0m), .B(B0m), .C(C0m), .D(D0m),
 386                                 .Z(F0)
 387                         );
 388                         LUT4 #(
 389                                 .INIT(LUT1_INITVAL)
 390                         ) lut4_1 (
 391                                 .A(A1m), .B(B1m), .C(C1m), .D(D1m),
 392                                 .Z(F1)
 393                         );
 394                         // LUT expansion muxes
 395                         PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
 396                         L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
 397                 end else if (MODE == "CCU2") begin
 398                         CCU2C #(
 399                                 .INIT0(LUT0_INITVAL),
 400                                 .INIT1(LUT1_INITVAL),
 401                                 .INJECT1_0(CCU2_INJECT1_0),
 402                                 .INJECT1_1(CCU2_INJECT1_1)
 403                   ) ccu2c_i (
 404                                 .CIN(FCI),
 405                                 .A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
 406                                 .A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
 407                                 .S0(F0), .S1(F1),
 408                                 .COUT(FCO)
 409                         );
 410                 end else if (MODE == "RAMW") begin
 411                         assign WDO0 = C1m;
 412                         assign WDO1 = A1m;
 413                         assign WDO2 = D1m;
 414                         assign WDO3 = B1m;
 415                         assign WADO0 = D0m;
 416                         assign WADO1 = B0m;
 417                         assign WADO2 = C0m;
 418                         assign WADO3 = A0m;
 419                 end else if (MODE == "DPRAM") begin
 420                         TRELLIS_RAM16X2 #(
 421                                 .INITVAL_0(permute_initval(LUT0_INITVAL)),
 422                                 .INITVAL_1(permute_initval(LUT1_INITVAL)),
 423                                 .WREMUX(WREMUX)
 424                         ) ram_i (
 425                                 .DI0(WD0), .DI1(WD1),
 426                                 .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
 427                                 .WRE(WRE), .WCK(WCK),
 428                                 .RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
 429                                 .DO0(F0), .DO1(F1)
 430                         );
 431                         // TODO: confirm RAD and INITVAL ordering
 432                         // DPRAM mode contract?
 433 `ifdef FORMAL
 434                         always @(*) begin
 435                                 assert(A0m==A1m);
 436                                 assert(B0m==B1m);
 437                                 assert(C0m==C1m);
 438                                 assert(D0m==D1m);
 439                         end
 440 `endif
 441                 end else begin
 442                         ERROR_UNKNOWN_SLICE_MODE error();
 443                 end
 444         endgenerate
 445
 446         // FF input selection muxes
 447         wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
 448         wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
 449         // Flipflops
 450         TRELLIS_FF #(
 451                 .GSR(GSR),
 452                 .CEMUX(CEMUX),
 453                 .CLKMUX(CLKMUX),
 454                 .LSRMUX(LSRMUX),
 455                 .SRMODE(SRMODE),
 456                 .REGSET(REG0_REGSET),
 457                 .LSRMODE(REG0_LSRMODE)
 458         ) ff_0 (
 459                 .CLK(CLK), .LSR(LSR), .CE(CE),
 460                 .DI(muxdi0), .M(M0),
 461                 .Q(Q0)
 462         );
 463         TRELLIS_FF #(
 464                 .GSR(GSR),
 465                 .CEMUX(CEMUX),
 466                 .CLKMUX(CLKMUX),
 467                 .LSRMUX(LSRMUX),
 468                 .SRMODE(SRMODE),
 469                 .REGSET(REG1_REGSET),
 470                 .LSRMODE(REG1_LSRMODE)
 471         ) ff_1 (
 472                 .CLK(CLK), .LSR(LSR), .CE(CE),
 473                 .DI(muxdi1), .M(M1),
 474                 .Q(Q1)
 475         );
 476 endmodule
 477
 478 (* blackbox *)
 479 module DP16KD(
 480   input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
 481   input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
 482   input CEA, OCEA, CLKA, WEA, RSTA,
 483   input CSA2, CSA1, CSA0,
 484   output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
 485
 486   input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
 487   input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
 488   input CEB, OCEB, CLKB, WEB, RSTB,
 489   input CSB2, CSB1, CSB0,
 490   output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 491 );
 492         parameter DATA_WIDTH_A = 18;
 493         parameter DATA_WIDTH_B = 18;
 494
 495         parameter REGMODE_A = "NOREG";
 496         parameter REGMODE_B = "NOREG";
 497
 498         parameter RESETMODE = "SYNC";
 499         parameter ASYNC_RESET_RELEASE = "SYNC";
 500
 501         parameter CSDECODE_A = "0b000";
 502         parameter CSDECODE_B = "0b000";
 503
 504         parameter WRITEMODE_A = "NORMAL";
 505         parameter WRITEMODE_B = "NORMAL";
 506
 507         parameter DIA17MUX = "DIA17";
 508         parameter DIA16MUX = "DIA16";
 509         parameter DIA15MUX = "DIA15";
 510         parameter DIA14MUX = "DIA14";
 511         parameter DIA13MUX = "DIA13";
 512         parameter DIA12MUX = "DIA12";
 513         parameter DIA11MUX = "DIA11";
 514         parameter DIA10MUX = "DIA10";
 515         parameter DIA9MUX = "DIA9";
 516         parameter DIA8MUX = "DIA8";
 517         parameter DIA7MUX = "DIA7";
 518         parameter DIA6MUX = "DIA6";
 519         parameter DIA5MUX = "DIA5";
 520         parameter DIA4MUX = "DIA4";
 521         parameter DIA3MUX = "DIA3";
 522         parameter DIA2MUX = "DIA2";
 523         parameter DIA1MUX = "DIA1";
 524         parameter DIA0MUX = "DIA0";
 525         parameter ADA13MUX = "ADA13";
 526         parameter ADA12MUX = "ADA12";
 527         parameter ADA11MUX = "ADA11";
 528         parameter ADA10MUX = "ADA10";
 529         parameter ADA9MUX = "ADA9";
 530         parameter ADA8MUX = "ADA8";
 531         parameter ADA7MUX = "ADA7";
 532         parameter ADA6MUX = "ADA6";
 533         parameter ADA5MUX = "ADA5";
 534         parameter ADA4MUX = "ADA4";
 535         parameter ADA3MUX = "ADA3";
 536         parameter ADA2MUX = "ADA2";
 537         parameter ADA1MUX = "ADA1";
 538         parameter ADA0MUX = "ADA0";
 539         parameter CEAMUX = "CEA";
 540         parameter OCEAMUX = "OCEA";
 541         parameter CLKAMUX = "CLKA";
 542         parameter WEAMUX = "WEA";
 543         parameter RSTAMUX = "RSTA";
 544         parameter CSA2MUX = "CSA2";
 545         parameter CSA1MUX = "CSA1";
 546         parameter CSA0MUX = "CSA0";
 547         parameter DOA17MUX = "DOA17";
 548         parameter DOA16MUX = "DOA16";
 549         parameter DOA15MUX = "DOA15";
 550         parameter DOA14MUX = "DOA14";
 551         parameter DOA13MUX = "DOA13";
 552         parameter DOA12MUX = "DOA12";
 553         parameter DOA11MUX = "DOA11";
 554         parameter DOA10MUX = "DOA10";
 555         parameter DOA9MUX = "DOA9";
 556         parameter DOA8MUX = "DOA8";
 557         parameter DOA7MUX = "DOA7";
 558         parameter DOA6MUX = "DOA6";
 559         parameter DOA5MUX = "DOA5";
 560         parameter DOA4MUX = "DOA4";
 561         parameter DOA3MUX = "DOA3";
 562         parameter DOA2MUX = "DOA2";
 563         parameter DOA1MUX = "DOA1";
 564         parameter DOA0MUX = "DOA0";
 565         parameter DIB17MUX = "DIB17";
 566         parameter DIB16MUX = "DIB16";
 567         parameter DIB15MUX = "DIB15";
 568         parameter DIB14MUX = "DIB14";
 569         parameter DIB13MUX = "DIB13";
 570         parameter DIB12MUX = "DIB12";
 571         parameter DIB11MUX = "DIB11";
 572         parameter DIB10MUX = "DIB10";
 573         parameter DIB9MUX = "DIB9";
 574         parameter DIB8MUX = "DIB8";
 575         parameter DIB7MUX = "DIB7";
 576         parameter DIB6MUX = "DIB6";
 577         parameter DIB5MUX = "DIB5";
 578         parameter DIB4MUX = "DIB4";
 579         parameter DIB3MUX = "DIB3";
 580         parameter DIB2MUX = "DIB2";
 581         parameter DIB1MUX = "DIB1";
 582         parameter DIB0MUX = "DIB0";
 583         parameter ADB13MUX = "ADB13";
 584         parameter ADB12MUX = "ADB12";
 585         parameter ADB11MUX = "ADB11";
 586         parameter ADB10MUX = "ADB10";
 587         parameter ADB9MUX = "ADB9";
 588         parameter ADB8MUX = "ADB8";
 589         parameter ADB7MUX = "ADB7";
 590         parameter ADB6MUX = "ADB6";
 591         parameter ADB5MUX = "ADB5";
 592         parameter ADB4MUX = "ADB4";
 593         parameter ADB3MUX = "ADB3";
 594         parameter ADB2MUX = "ADB2";
 595         parameter ADB1MUX = "ADB1";
 596         parameter ADB0MUX = "ADB0";
 597         parameter CEBMUX = "CEB";
 598         parameter OCEBMUX = "OCEB";
 599         parameter CLKBMUX = "CLKB";
 600         parameter WEBMUX = "WEB";
 601         parameter RSTBMUX = "RSTB";
 602         parameter CSB2MUX = "CSB2";
 603         parameter CSB1MUX = "CSB1";
 604         parameter CSB0MUX = "CSB0";
 605         parameter DOB17MUX = "DOB17";
 606         parameter DOB16MUX = "DOB16";
 607         parameter DOB15MUX = "DOB15";
 608         parameter DOB14MUX = "DOB14";
 609         parameter DOB13MUX = "DOB13";
 610         parameter DOB12MUX = "DOB12";
 611         parameter DOB11MUX = "DOB11";
 612         parameter DOB10MUX = "DOB10";
 613         parameter DOB9MUX = "DOB9";
 614         parameter DOB8MUX = "DOB8";
 615         parameter DOB7MUX = "DOB7";
 616         parameter DOB6MUX = "DOB6";
 617         parameter DOB5MUX = "DOB5";
 618         parameter DOB4MUX = "DOB4";
 619         parameter DOB3MUX = "DOB3";
 620         parameter DOB2MUX = "DOB2";
 621         parameter DOB1MUX = "DOB1";
 622         parameter DOB0MUX = "DOB0";
 623
 624         parameter WID = 0;
 625
 626         parameter GSR = "ENABLED";
 627
 628         parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 629         parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 630         parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 631         parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 632         parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 633         parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 634         parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 635         parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 636         parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 637         parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 638         parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 639         parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 640         parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 641         parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 642         parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 643         parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 644         parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 645         parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 646         parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 647         parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 648         parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 649         parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 650         parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 651         parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 652         parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 653         parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 654         parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 655         parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 656         parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 657         parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 658         parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 659         parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 660         parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 661         parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 662         parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 663         parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 664         parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 665         parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 666         parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 667         parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 668         parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 669         parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 670         parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 671         parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 672         parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 673         parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 674         parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 675         parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 676         parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 677         parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 678         parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 679         parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 680         parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 681         parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 682         parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 683         parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 684         parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 685         parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 686         parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 687         parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 688         parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 689         parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 690         parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 691         parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 692 endmodule
 693
 694 `ifndef NO_INCLUDES
 695
 696 `include "cells_ff.vh"
 697 `include "cells_io.vh"
 698
 699 `endif