2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 David Shah <dave@ds0.me>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
27 PRIVATE_NAMESPACE_BEGIN
29 struct SynthEcp5Pass
: public ScriptPass
31 SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
33 void on_register() YS_OVERRIDE
35 RTLIL::constpad
["synth_ecp5.abc9.W"] = "300";
38 void help() YS_OVERRIDE
40 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
42 log(" synth_ecp5 [options]\n");
44 log("This command runs synthesis for ECP5 FPGAs.\n");
46 log(" -top <module>\n");
47 log(" use the specified module as top module\n");
49 log(" -blif <file>\n");
50 log(" write the design to the specified BLIF file. writing of an output file\n");
51 log(" is omitted if this parameter is not specified.\n");
53 log(" -edif <file>\n");
54 log(" write the design to the specified EDIF file. writing of an output file\n");
55 log(" is omitted if this parameter is not specified.\n");
57 log(" -json <file>\n");
58 log(" write the design to the specified JSON file. writing of an output file\n");
59 log(" is omitted if this parameter is not specified.\n");
61 log(" -run <from_label>:<to_label>\n");
62 log(" only run the commands between the labels (see below). an empty\n");
63 log(" from label is synonymous to 'begin', and empty to label is\n");
64 log(" synonymous to the end of the command list.\n");
67 log(" do not flatten design before synthesis\n");
70 log(" run 'abc'/'abc9' with -dff option\n");
73 log(" run 'abc' with '-dff -D 1' options\n");
76 log(" do not use CCU2 cells in output netlist\n");
79 log(" do not use flipflops with CE in output netlist\n");
82 log(" do not use block RAM cells in output netlist\n");
85 log(" do not use LUT RAM cells in output netlist\n");
88 log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
91 log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n");
94 log(" run two passes of 'abc' for slightly improved logic density\n");
97 log(" use new ABC9 flow (EXPERIMENTAL)\n");
100 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
101 log(" (this feature is experimental and incomplete)\n");
104 log(" do not map multipliers to MULT18X18D\n");
107 log("The following commands are executed by this synthesis command:\n");
112 string top_opt
, blif_file
, edif_file
, json_file
;
113 bool noccu2
, nodffe
, nobram
, nolutram
, nowidelut
, asyncprld
, flatten
, dff
, retime
, abc2
, abc9
, nodsp
, vpr
;
115 void clear_flags() YS_OVERRIDE
117 top_opt
= "-auto-top";
136 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
138 string run_from
, run_to
;
142 for (argidx
= 1; argidx
< args
.size(); argidx
++)
144 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
145 top_opt
= "-top " + args
[++argidx
];
148 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
149 blif_file
= args
[++argidx
];
152 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
153 edif_file
= args
[++argidx
];
156 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
157 json_file
= args
[++argidx
];
160 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
161 size_t pos
= args
[argidx
+1].find(':');
162 if (pos
== std::string::npos
)
164 run_from
= args
[++argidx
].substr(0, pos
);
165 run_to
= args
[argidx
].substr(pos
+1);
168 if (args
[argidx
] == "-flatten") {
172 if (args
[argidx
] == "-noflatten") {
176 if (args
[argidx
] == "-dff") {
180 if (args
[argidx
] == "-retime") {
184 if (args
[argidx
] == "-noccu2") {
188 if (args
[argidx
] == "-nodffe") {
192 if (args
[argidx
] == "-nobram") {
196 if (args
[argidx
] == "-asyncprld") {
200 if (args
[argidx
] == "-nolutram" || /*deprecated alias*/ args
[argidx
] == "-nodram") {
204 if (args
[argidx
] == "-nowidelut" || /*deprecated alias*/ args
[argidx
] == "-nomux") {
208 if (args
[argidx
] == "-abc2") {
212 if (args
[argidx
] == "-vpr") {
216 if (args
[argidx
] == "-abc9") {
220 if (args
[argidx
] == "-nodsp") {
226 extra_args(args
, argidx
, design
);
228 if (!design
->full_selection())
229 log_cmd_error("This command only operates on fully selected designs!\n");
232 log_cmd_error("-retime option not currently compatible with -abc9!\n");
234 log_header(design
, "Executing SYNTH_ECP5 pass.\n");
237 run_script(design
, run_from
, run_to
);
242 void script() YS_OVERRIDE
244 if (check_label("begin"))
246 run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
247 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
250 if (check_label("coarse"))
253 if (flatten
|| help_mode
)
255 run("tribuf -logic");
265 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
269 run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
270 run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
276 run("memory -nomap");
280 if (!nobram
&& check_label("map_bram", "(skip if -nobram)"))
282 run("memory_bram -rules +/ecp5/brams.txt");
283 run("techmap -map +/ecp5/brams_map.v");
286 if (!nolutram
&& check_label("map_lutram", "(skip if -nolutram)"))
288 run("memory_bram -rules +/ecp5/lutrams.txt");
289 run("techmap -map +/ecp5/lutrams_map.v");
292 if (check_label("map_ffram"))
294 run("opt -fast -mux_undef -undriven -fine");
295 run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
296 "-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
297 "-attr syn_romstyle=auto -attr syn_romstyle=logic");
298 run("opt -undriven -fine");
301 if (check_label("map_gates"))
306 run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
308 if (retime
|| help_mode
)
309 run("abc -dff -D 1", "(only if -retime)");
312 if (check_label("map_ffs"))
317 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
318 if ((abc9
&& dff
) || help_mode
)
319 run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
320 run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode
? "[-D ASYNC_PRLD]" : (asyncprld
? "-D ASYNC_PRLD" : "")));
321 run("opt_expr -undriven -mux_undef");
325 run("attrmvcp -copy -attr syn_useioff");
329 if (check_label("map_luts"))
331 if (abc2
|| help_mode
)
332 run("abc", " (only if -abc2)");
333 if (!asyncprld
|| help_mode
)
334 run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)");
337 std::string abc9_opts
;
339 abc9_opts
+= " -maxlut 4";
340 std::string k
= "synth_ecp5.abc9.W";
341 if (active_design
&& active_design
->scratchpad
.count(k
))
342 abc9_opts
+= stringf(" -W %s", active_design
->scratchpad_get_string(k
).c_str());
344 abc9_opts
+= stringf(" -W %s", RTLIL::constpad
.at(k
).c_str());
346 abc9_opts
+= " -maxlut 4";
348 abc9_opts
+= " -dff";
349 run("abc9" + abc9_opts
);
351 std::string abc_args
= " -dress";
353 abc_args
+= " -lut 4";
355 abc_args
+= " -lut 4:7";
358 run("abc" + abc_args
);
363 if (check_label("map_cells"))
366 run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
368 run("techmap -map +/ecp5/cells_map.v");
369 run("opt_lut_ins -tech ecp5");
373 if (check_label("check"))
376 run("hierarchy -check");
378 run("check -noinit");
381 if (check_label("blif"))
383 if (!blif_file
.empty() || help_mode
) {
384 if (vpr
|| help_mode
) {
385 run(stringf("opt_clean -purge"),
387 run(stringf("write_blif -attr -cname -conn -param %s",
388 help_mode
? "<file-name>" : blif_file
.c_str()),
392 run(stringf("write_blif -gates -attr -param %s",
393 help_mode
? "<file-name>" : blif_file
.c_str()),
398 if (check_label("edif"))
400 if (!edif_file
.empty() || help_mode
)
401 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
404 if (check_label("json"))
406 if (!json_file
.empty() || help_mode
)
407 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
412 PRIVATE_NAMESPACE_END