2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 Clifford Wolf <dave@ds0.me>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
27 PRIVATE_NAMESPACE_BEGIN
29 struct SynthEcp5Pass
: public ScriptPass
31 SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
33 void help() YS_OVERRIDE
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
37 log(" synth_ecp5 [options]\n");
39 log("This command runs synthesis for ECP5 FPGAs.\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
44 log(" -blif <file>\n");
45 log(" write the design to the specified BLIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
48 log(" -edif <file>\n");
49 log(" write the design to the specified EDIF file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
52 log(" -json <file>\n");
53 log(" write the design to the specified JSON file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
62 log(" do not flatten design before synthesis\n");
65 log(" run 'abc' with -dff option\n");
68 log(" do not use CCU2 cells in output netlist\n");
71 log(" do not use flipflops with CE in output netlist\n");
74 log(" do not use BRAM cells in output netlist\n");
77 log(" do not use distributed RAM cells in output netlist\n");
80 log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
83 log(" run two passes of 'abc' for slightly improved logic density\n");
86 log(" use new ABC9 flow (EXPERIMENTAL)\n");
89 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
90 log(" (this feature is experimental and incomplete)\n");
93 log("The following commands are executed by this synthesis command:\n");
98 string top_opt
, blif_file
, edif_file
, json_file
;
99 bool noccu2
, nodffe
, nobram
, nodram
, nomux
, flatten
, retime
, abc2
, abc9
, vpr
;
101 void clear_flags() YS_OVERRIDE
103 top_opt
= "-auto-top";
119 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
121 string run_from
, run_to
;
125 for (argidx
= 1; argidx
< args
.size(); argidx
++)
127 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
128 top_opt
= "-top " + args
[++argidx
];
131 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
132 blif_file
= args
[++argidx
];
135 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
136 edif_file
= args
[++argidx
];
139 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
140 json_file
= args
[++argidx
];
143 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
144 size_t pos
= args
[argidx
+1].find(':');
145 if (pos
== std::string::npos
)
147 run_from
= args
[++argidx
].substr(0, pos
);
148 run_to
= args
[argidx
].substr(pos
+1);
151 if (args
[argidx
] == "-flatten") {
155 if (args
[argidx
] == "-noflatten") {
159 if (args
[argidx
] == "-retime") {
163 if (args
[argidx
] == "-noccu2") {
167 if (args
[argidx
] == "-nodffe") {
171 if (args
[argidx
] == "-nobram") {
175 if (args
[argidx
] == "-nodram") {
179 if (args
[argidx
] == "-nomux") {
183 if (args
[argidx
] == "-abc2") {
187 if (args
[argidx
] == "-vpr") {
191 if (args
[argidx
] == "-abc9") {
197 extra_args(args
, argidx
, design
);
199 if (!design
->full_selection())
200 log_cmd_error("This command only operates on fully selected designs!\n");
202 log_header(design
, "Executing SYNTH_ECP5 pass.\n");
205 run_script(design
, run_from
, run_to
);
210 void script() YS_OVERRIDE
212 if (check_label("begin"))
214 run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
215 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
218 if (flatten
&& check_label("flatten", "(unless -noflatten)"))
222 run("tribuf -logic");
226 if (check_label("coarse"))
228 run("synth -run coarse");
231 if (!nobram
&& check_label("bram", "(skip if -nobram)"))
233 run("memory_bram -rules +/ecp5/bram.txt");
234 run("techmap -map +/ecp5/brams_map.v");
237 if (!nodram
&& check_label("dram", "(skip if -nodram)"))
239 run("memory_bram -rules +/ecp5/dram.txt");
240 run("techmap -map +/ecp5/drams_map.v");
243 if (check_label("fine"))
245 run("opt -fast -mux_undef -undriven -fine");
247 run("opt -undriven -fine");
251 run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
252 if (retime
|| help_mode
)
253 run("abc -dff", "(only if -retime)");
256 if (check_label("map_ffs"))
262 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
263 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
264 run("opt_expr -undriven -mux_undef");
269 if (check_label("map_luts"))
271 if (abc2
|| help_mode
) {
272 run("abc", " (only if -abc2)");
274 run("techmap -map +/ecp5/latches_map.v");
276 run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
279 run("abc -lut 4 -dress");
281 run("abc -lut 4:7 -dress");
287 if (check_label("map_cells"))
290 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
292 run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
297 if (check_label("check"))
299 run("hierarchy -check");
301 run("check -noinit");
304 if (check_label("blif"))
306 if (!blif_file
.empty() || help_mode
) {
307 if (vpr
|| help_mode
) {
308 run(stringf("opt_clean -purge"),
310 run(stringf("write_blif -attr -cname -conn -param %s",
311 help_mode
? "<file-name>" : blif_file
.c_str()),
315 run(stringf("write_blif -gates -attr -param %s",
316 help_mode
? "<file-name>" : blif_file
.c_str()),
321 if (check_label("edif"))
323 if (!edif_file
.empty() || help_mode
)
324 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
327 if (check_label("json"))
329 if (!json_file
.empty() || help_mode
)
330 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
335 PRIVATE_NAMESPACE_END