synth_{ice40,ecp5}: more sensible pass label naming.
[yosys.git] / techlibs / ecp5 / synth_ecp5.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 David Shah <dave@ds0.me>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 struct SynthEcp5Pass : public ScriptPass
30 {
31 SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
32
33 void help() YS_OVERRIDE
34 {
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log("\n");
37 log(" synth_ecp5 [options]\n");
38 log("\n");
39 log("This command runs synthesis for ECP5 FPGAs.\n");
40 log("\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
43 log("\n");
44 log(" -blif <file>\n");
45 log(" write the design to the specified BLIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
47 log("\n");
48 log(" -edif <file>\n");
49 log(" write the design to the specified EDIF file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
51 log("\n");
52 log(" -json <file>\n");
53 log(" write the design to the specified JSON file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
55 log("\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
60 log("\n");
61 log(" -noflatten\n");
62 log(" do not flatten design before synthesis\n");
63 log("\n");
64 log(" -retime\n");
65 log(" run 'abc' with -dff option\n");
66 log("\n");
67 log(" -noccu2\n");
68 log(" do not use CCU2 cells in output netlist\n");
69 log("\n");
70 log(" -nodffe\n");
71 log(" do not use flipflops with CE in output netlist\n");
72 log("\n");
73 log(" -nobram\n");
74 log(" do not use BRAM cells in output netlist\n");
75 log("\n");
76 log(" -nodram\n");
77 log(" do not use distributed RAM cells in output netlist\n");
78 log("\n");
79 log(" -nowidelut\n");
80 log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
81 log("\n");
82 log(" -abc2\n");
83 log(" run two passes of 'abc' for slightly improved logic density\n");
84 log("\n");
85 log(" -abc9\n");
86 log(" use new ABC9 flow (EXPERIMENTAL)\n");
87 log("\n");
88 log(" -vpr\n");
89 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
90 log(" (this feature is experimental and incomplete)\n");
91 log("\n");
92 log("\n");
93 log("The following commands are executed by this synthesis command:\n");
94 help_script();
95 log("\n");
96 }
97
98 string top_opt, blif_file, edif_file, json_file;
99 bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
100
101 void clear_flags() YS_OVERRIDE
102 {
103 top_opt = "-auto-top";
104 blif_file = "";
105 edif_file = "";
106 json_file = "";
107 noccu2 = false;
108 nodffe = false;
109 nobram = false;
110 nodram = false;
111 nowidelut = false;
112 flatten = true;
113 retime = false;
114 abc2 = false;
115 vpr = false;
116 abc9 = false;
117 }
118
119 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
120 {
121 string run_from, run_to;
122 clear_flags();
123
124 size_t argidx;
125 for (argidx = 1; argidx < args.size(); argidx++)
126 {
127 if (args[argidx] == "-top" && argidx+1 < args.size()) {
128 top_opt = "-top " + args[++argidx];
129 continue;
130 }
131 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
132 blif_file = args[++argidx];
133 continue;
134 }
135 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
136 edif_file = args[++argidx];
137 continue;
138 }
139 if (args[argidx] == "-json" && argidx+1 < args.size()) {
140 json_file = args[++argidx];
141 continue;
142 }
143 if (args[argidx] == "-run" && argidx+1 < args.size()) {
144 size_t pos = args[argidx+1].find(':');
145 if (pos == std::string::npos)
146 break;
147 run_from = args[++argidx].substr(0, pos);
148 run_to = args[argidx].substr(pos+1);
149 continue;
150 }
151 if (args[argidx] == "-flatten") {
152 flatten = true;
153 continue;
154 }
155 if (args[argidx] == "-noflatten") {
156 flatten = false;
157 continue;
158 }
159 if (args[argidx] == "-retime") {
160 retime = true;
161 continue;
162 }
163 if (args[argidx] == "-noccu2") {
164 noccu2 = true;
165 continue;
166 }
167 if (args[argidx] == "-nodffe") {
168 nodffe = true;
169 continue;
170 }
171 if (args[argidx] == "-nobram") {
172 nobram = true;
173 continue;
174 }
175 if (args[argidx] == "-nodram") {
176 nodram = true;
177 continue;
178 }
179 if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
180 nowidelut = true;
181 continue;
182 }
183 if (args[argidx] == "-abc2") {
184 abc2 = true;
185 continue;
186 }
187 if (args[argidx] == "-vpr") {
188 vpr = true;
189 continue;
190 }
191 if (args[argidx] == "-abc9") {
192 abc9 = true;
193 continue;
194 }
195 break;
196 }
197 extra_args(args, argidx, design);
198
199 if (!design->full_selection())
200 log_cmd_error("This command only operates on fully selected designs!\n");
201
202 if (abc9 && retime)
203 log_cmd_error("-retime option not currently compatible with -abc9!\n");
204
205 log_header(design, "Executing SYNTH_ECP5 pass.\n");
206 log_push();
207
208 run_script(design, run_from, run_to);
209
210 log_pop();
211 }
212
213 void script() YS_OVERRIDE
214 {
215 if (check_label("begin"))
216 {
217 run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
218 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
219 }
220
221 if (flatten && check_label("flatten", "(unless -noflatten)"))
222 {
223 run("proc");
224 run("flatten");
225 run("tribuf -logic");
226 run("deminout");
227 }
228
229 if (check_label("coarse"))
230 {
231 run("synth -run coarse");
232 }
233
234 if (!nobram && check_label("map_bram", "(skip if -nobram)"))
235 {
236 run("memory_bram -rules +/ecp5/bram.txt");
237 run("techmap -map +/ecp5/brams_map.v");
238 }
239
240 if (!nodram && check_label("map_dram", "(skip if -nodram)"))
241 {
242 run("memory_bram -rules +/ecp5/dram.txt");
243 run("techmap -map +/ecp5/drams_map.v");
244 }
245
246 if (check_label("map_ffram"))
247 {
248 run("opt -fast -mux_undef -undriven -fine");
249 run("memory_map");
250 run("opt -undriven -fine");
251 }
252
253 if (check_label("map_gates"))
254 {
255 if (noccu2)
256 run("techmap");
257 else
258 run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
259 if (retime || help_mode)
260 run("abc -dff", "(only if -retime)");
261 }
262
263 if (check_label("map_ffs"))
264 {
265 run("dffsr2dff");
266 run("dff2dffs");
267 run("opt_clean");
268 if (!nodffe)
269 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
270 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
271 run("opt_expr -undriven -mux_undef");
272 run("simplemap");
273 run("ecp5_ffinit");
274 }
275
276 if (check_label("map_luts"))
277 {
278 if (abc2 || help_mode) {
279 run("abc", " (only if -abc2)");
280 }
281 run("techmap -map +/ecp5/latches_map.v");
282 if (abc9) {
283 if (nowidelut)
284 run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
285 else
286 run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
287 } else {
288 if (nowidelut)
289 run("abc -lut 4 -dress");
290 else
291 run("abc -lut 4:7 -dress");
292 }
293 run("clean");
294 }
295
296 if (check_label("map_cells"))
297 {
298 if (vpr)
299 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
300 else
301 run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
302
303 run("clean");
304 }
305
306 if (check_label("check"))
307 {
308 run("hierarchy -check");
309 run("stat");
310 run("check -noinit");
311 }
312
313 if (check_label("blif"))
314 {
315 if (!blif_file.empty() || help_mode) {
316 if (vpr || help_mode) {
317 run(stringf("opt_clean -purge"),
318 " (vpr mode)");
319 run(stringf("write_blif -attr -cname -conn -param %s",
320 help_mode ? "<file-name>" : blif_file.c_str()),
321 " (vpr mode)");
322 }
323 if (!vpr)
324 run(stringf("write_blif -gates -attr -param %s",
325 help_mode ? "<file-name>" : blif_file.c_str()),
326 " (non-vpr mode)");
327 }
328 }
329
330 if (check_label("edif"))
331 {
332 if (!edif_file.empty() || help_mode)
333 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
334 }
335
336 if (check_label("json"))
337 {
338 if (!json_file.empty() || help_mode)
339 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
340 }
341 }
342 } SynthEcp5Pass;
343
344 PRIVATE_NAMESPACE_END