Merge pull request #1494 from whitequark/write_verilog-extmem
[yosys.git] / techlibs / ecp5 / synth_ecp5.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 David Shah <dave@ds0.me>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 struct SynthEcp5Pass : public ScriptPass
30 {
31 SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
32
33 void help() YS_OVERRIDE
34 {
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log("\n");
37 log(" synth_ecp5 [options]\n");
38 log("\n");
39 log("This command runs synthesis for ECP5 FPGAs.\n");
40 log("\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
43 log("\n");
44 log(" -blif <file>\n");
45 log(" write the design to the specified BLIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
47 log("\n");
48 log(" -edif <file>\n");
49 log(" write the design to the specified EDIF file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
51 log("\n");
52 log(" -json <file>\n");
53 log(" write the design to the specified JSON file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
55 log("\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
60 log("\n");
61 log(" -noflatten\n");
62 log(" do not flatten design before synthesis\n");
63 log("\n");
64 log(" -retime\n");
65 log(" run 'abc' with -dff option\n");
66 log("\n");
67 log(" -noccu2\n");
68 log(" do not use CCU2 cells in output netlist\n");
69 log("\n");
70 log(" -nodffe\n");
71 log(" do not use flipflops with CE in output netlist\n");
72 log("\n");
73 log(" -nobram\n");
74 log(" do not use block RAM cells in output netlist\n");
75 log("\n");
76 log(" -nolutram\n");
77 log(" do not use LUT RAM cells in output netlist\n");
78 log("\n");
79 log(" -nowidelut\n");
80 log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
81 log("\n");
82 log(" -abc2\n");
83 log(" run two passes of 'abc' for slightly improved logic density\n");
84 log("\n");
85 log(" -abc9\n");
86 log(" use new ABC9 flow (EXPERIMENTAL)\n");
87 log("\n");
88 log(" -vpr\n");
89 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
90 log(" (this feature is experimental and incomplete)\n");
91 log("\n");
92 log(" -nodsp\n");
93 log(" do not map multipliers to MULT18X18D\n");
94 log("\n");
95 log("\n");
96 log("The following commands are executed by this synthesis command:\n");
97 help_script();
98 log("\n");
99 }
100
101 string top_opt, blif_file, edif_file, json_file;
102 bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr;
103
104 void clear_flags() YS_OVERRIDE
105 {
106 top_opt = "-auto-top";
107 blif_file = "";
108 edif_file = "";
109 json_file = "";
110 noccu2 = false;
111 nodffe = false;
112 nobram = false;
113 nolutram = false;
114 nowidelut = false;
115 flatten = true;
116 retime = false;
117 abc2 = false;
118 vpr = false;
119 abc9 = false;
120 nodsp = false;
121 }
122
123 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
124 {
125 string run_from, run_to;
126 clear_flags();
127
128 size_t argidx;
129 for (argidx = 1; argidx < args.size(); argidx++)
130 {
131 if (args[argidx] == "-top" && argidx+1 < args.size()) {
132 top_opt = "-top " + args[++argidx];
133 continue;
134 }
135 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
136 blif_file = args[++argidx];
137 continue;
138 }
139 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
140 edif_file = args[++argidx];
141 continue;
142 }
143 if (args[argidx] == "-json" && argidx+1 < args.size()) {
144 json_file = args[++argidx];
145 continue;
146 }
147 if (args[argidx] == "-run" && argidx+1 < args.size()) {
148 size_t pos = args[argidx+1].find(':');
149 if (pos == std::string::npos)
150 break;
151 run_from = args[++argidx].substr(0, pos);
152 run_to = args[argidx].substr(pos+1);
153 continue;
154 }
155 if (args[argidx] == "-flatten") {
156 flatten = true;
157 continue;
158 }
159 if (args[argidx] == "-noflatten") {
160 flatten = false;
161 continue;
162 }
163 if (args[argidx] == "-retime") {
164 retime = true;
165 continue;
166 }
167 if (args[argidx] == "-noccu2") {
168 noccu2 = true;
169 continue;
170 }
171 if (args[argidx] == "-nodffe") {
172 nodffe = true;
173 continue;
174 }
175 if (args[argidx] == "-nobram") {
176 nobram = true;
177 continue;
178 }
179 if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
180 nolutram = true;
181 continue;
182 }
183 if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
184 nowidelut = true;
185 continue;
186 }
187 if (args[argidx] == "-abc2") {
188 abc2 = true;
189 continue;
190 }
191 if (args[argidx] == "-vpr") {
192 vpr = true;
193 continue;
194 }
195 if (args[argidx] == "-abc9") {
196 abc9 = true;
197 continue;
198 }
199 if (args[argidx] == "-nodsp") {
200 nodsp = true;
201 continue;
202 }
203 break;
204 }
205 extra_args(args, argidx, design);
206
207 if (!design->full_selection())
208 log_cmd_error("This command only operates on fully selected designs!\n");
209
210 if (abc9 && retime)
211 log_cmd_error("-retime option not currently compatible with -abc9!\n");
212
213 log_header(design, "Executing SYNTH_ECP5 pass.\n");
214 log_push();
215
216 run_script(design, run_from, run_to);
217
218 log_pop();
219 }
220
221 void script() YS_OVERRIDE
222 {
223 if (check_label("begin"))
224 {
225 run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
226 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
227 }
228
229 if (check_label("coarse"))
230 {
231 run("proc");
232 if (flatten || help_mode)
233 run("flatten");
234 run("tribuf -logic");
235 run("deminout");
236 run("opt_expr");
237 run("opt_clean");
238 run("check");
239 run("opt");
240 run("wreduce");
241 run("peepopt");
242 run("opt_clean");
243 run("share");
244 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
245 run("opt_expr");
246 run("opt_clean");
247 if (!nodsp) {
248 run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
249 run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
250 }
251 run("alumacc");
252 run("opt");
253 run("fsm");
254 run("opt -fast");
255 run("memory -nomap");
256 run("opt_clean");
257 }
258
259 if (!nobram && check_label("map_bram", "(skip if -nobram)"))
260 {
261 run("memory_bram -rules +/ecp5/bram.txt");
262 run("techmap -map +/ecp5/brams_map.v");
263 }
264
265 if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
266 {
267 run("memory_bram -rules +/ecp5/lutram.txt");
268 run("techmap -map +/ecp5/lutrams_map.v");
269 }
270
271 if (check_label("map_ffram"))
272 {
273 run("opt -fast -mux_undef -undriven -fine");
274 run("memory_map");
275 run("opt -undriven -fine");
276 }
277
278 if (check_label("map_gates"))
279 {
280 if (noccu2)
281 run("techmap");
282 else
283 run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
284 if (retime || help_mode)
285 run("abc -dff", "(only if -retime)");
286 }
287
288 if (check_label("map_ffs"))
289 {
290 run("dffsr2dff");
291 run("dff2dffs");
292 run("opt_clean");
293 if (!nodffe)
294 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
295 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
296 run("opt_expr -undriven -mux_undef");
297 run("simplemap");
298 run("ecp5_ffinit");
299 run("ecp5_gsr");
300 run("attrmvcp -copy -attr syn_useioff");
301 run("opt_clean");
302 }
303
304 if (check_label("map_luts"))
305 {
306 if (abc2 || help_mode) {
307 run("abc", " (only if -abc2)");
308 }
309 std::string techmap_args = "-map +/ecp5/latches_map.v";
310 if (abc9)
311 techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
312 run("techmap " + techmap_args);
313
314 if (abc9) {
315 run("read_verilog -icells -lib +/ecp5/abc9_model.v");
316 if (nowidelut)
317 run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
318 else
319 run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
320 run("techmap -map +/ecp5/abc9_unmap.v");
321 } else {
322 if (nowidelut)
323 run("abc -lut 4 -dress");
324 else
325 run("abc -lut 4:7 -dress");
326 }
327 run("clean");
328 }
329
330 if (check_label("map_cells"))
331 {
332 if (vpr)
333 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
334 else
335 run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
336
337 run("clean");
338 }
339
340 if (check_label("check"))
341 {
342 run("autoname");
343 run("hierarchy -check");
344 run("stat");
345 run("check -noinit");
346 }
347
348 if (check_label("blif"))
349 {
350 if (!blif_file.empty() || help_mode) {
351 if (vpr || help_mode) {
352 run(stringf("opt_clean -purge"),
353 " (vpr mode)");
354 run(stringf("write_blif -attr -cname -conn -param %s",
355 help_mode ? "<file-name>" : blif_file.c_str()),
356 " (vpr mode)");
357 }
358 if (!vpr)
359 run(stringf("write_blif -gates -attr -param %s",
360 help_mode ? "<file-name>" : blif_file.c_str()),
361 " (non-vpr mode)");
362 }
363 }
364
365 if (check_label("edif"))
366 {
367 if (!edif_file.empty() || help_mode)
368 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
369 }
370
371 if (check_label("json"))
372 {
373 if (!json_file.empty() || help_mode)
374 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
375 }
376 }
377 } SynthEcp5Pass;
378
379 PRIVATE_NAMESPACE_END