Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
[yosys.git] / techlibs / ecp5 / synth_ecp5.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 David Shah <dave@ds0.me>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 struct SynthEcp5Pass : public ScriptPass
30 {
31 SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
32
33 void help() YS_OVERRIDE
34 {
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log("\n");
37 log(" synth_ecp5 [options]\n");
38 log("\n");
39 log("This command runs synthesis for ECP5 FPGAs.\n");
40 log("\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
43 log("\n");
44 log(" -blif <file>\n");
45 log(" write the design to the specified BLIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
47 log("\n");
48 log(" -edif <file>\n");
49 log(" write the design to the specified EDIF file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
51 log("\n");
52 log(" -json <file>\n");
53 log(" write the design to the specified JSON file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
55 log("\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
60 log("\n");
61 log(" -noflatten\n");
62 log(" do not flatten design before synthesis\n");
63 log("\n");
64 log(" -retime\n");
65 log(" run 'abc' with -dff option\n");
66 log("\n");
67 log(" -noccu2\n");
68 log(" do not use CCU2 cells in output netlist\n");
69 log("\n");
70 log(" -nodffe\n");
71 log(" do not use flipflops with CE in output netlist\n");
72 log("\n");
73 log(" -nobram\n");
74 log(" do not use block RAM cells in output netlist\n");
75 log("\n");
76 log(" -nolutram\n");
77 log(" do not use LUT RAM cells in output netlist\n");
78 log("\n");
79 log(" -nowidelut\n");
80 log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
81 log("\n");
82 log(" -asyncprld\n");
83 log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n");
84 log("\n");
85 log(" -abc2\n");
86 log(" run two passes of 'abc' for slightly improved logic density\n");
87 log("\n");
88 log(" -abc9\n");
89 log(" use new ABC9 flow (EXPERIMENTAL)\n");
90 log("\n");
91 log(" -vpr\n");
92 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
93 log(" (this feature is experimental and incomplete)\n");
94 log("\n");
95 log(" -nodsp\n");
96 log(" do not map multipliers to MULT18X18D\n");
97 log("\n");
98 log("\n");
99 log("The following commands are executed by this synthesis command:\n");
100 help_script();
101 log("\n");
102 }
103
104 string top_opt, blif_file, edif_file, json_file;
105 bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr;
106
107 void clear_flags() YS_OVERRIDE
108 {
109 top_opt = "-auto-top";
110 blif_file = "";
111 edif_file = "";
112 json_file = "";
113 noccu2 = false;
114 nodffe = false;
115 nobram = false;
116 nolutram = false;
117 nowidelut = false;
118 asyncprld = false;
119 flatten = true;
120 retime = false;
121 abc2 = false;
122 vpr = false;
123 abc9 = false;
124 nodsp = false;
125 }
126
127 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
128 {
129 string run_from, run_to;
130 clear_flags();
131
132 size_t argidx;
133 for (argidx = 1; argidx < args.size(); argidx++)
134 {
135 if (args[argidx] == "-top" && argidx+1 < args.size()) {
136 top_opt = "-top " + args[++argidx];
137 continue;
138 }
139 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
140 blif_file = args[++argidx];
141 continue;
142 }
143 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
144 edif_file = args[++argidx];
145 continue;
146 }
147 if (args[argidx] == "-json" && argidx+1 < args.size()) {
148 json_file = args[++argidx];
149 continue;
150 }
151 if (args[argidx] == "-run" && argidx+1 < args.size()) {
152 size_t pos = args[argidx+1].find(':');
153 if (pos == std::string::npos)
154 break;
155 run_from = args[++argidx].substr(0, pos);
156 run_to = args[argidx].substr(pos+1);
157 continue;
158 }
159 if (args[argidx] == "-flatten") {
160 flatten = true;
161 continue;
162 }
163 if (args[argidx] == "-noflatten") {
164 flatten = false;
165 continue;
166 }
167 if (args[argidx] == "-retime") {
168 retime = true;
169 continue;
170 }
171 if (args[argidx] == "-noccu2") {
172 noccu2 = true;
173 continue;
174 }
175 if (args[argidx] == "-nodffe") {
176 nodffe = true;
177 continue;
178 }
179 if (args[argidx] == "-nobram") {
180 nobram = true;
181 continue;
182 }
183 if (args[argidx] == "-asyncprld") {
184 asyncprld = true;
185 continue;
186 }
187 if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
188 nolutram = true;
189 continue;
190 }
191 if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
192 nowidelut = true;
193 continue;
194 }
195 if (args[argidx] == "-abc2") {
196 abc2 = true;
197 continue;
198 }
199 if (args[argidx] == "-vpr") {
200 vpr = true;
201 continue;
202 }
203 if (args[argidx] == "-abc9") {
204 abc9 = true;
205 continue;
206 }
207 if (args[argidx] == "-nodsp") {
208 nodsp = true;
209 continue;
210 }
211 break;
212 }
213 extra_args(args, argidx, design);
214
215 if (!design->full_selection())
216 log_cmd_error("This command only operates on fully selected designs!\n");
217
218 if (abc9 && retime)
219 log_cmd_error("-retime option not currently compatible with -abc9!\n");
220
221 log_header(design, "Executing SYNTH_ECP5 pass.\n");
222 log_push();
223
224 run_script(design, run_from, run_to);
225
226 log_pop();
227 }
228
229 void script() YS_OVERRIDE
230 {
231 if (check_label("begin"))
232 {
233 run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
234 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
235 }
236
237 if (check_label("coarse"))
238 {
239 run("proc");
240 if (flatten || help_mode)
241 run("flatten");
242 run("tribuf -logic");
243 run("deminout");
244 run("opt_expr");
245 run("opt_clean");
246 run("check");
247 run("opt");
248 run("wreduce");
249 run("peepopt");
250 run("opt_clean");
251 run("share");
252 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
253 run("opt_expr");
254 run("opt_clean");
255 if (!nodsp) {
256 run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
257 run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
258 }
259 run("alumacc");
260 run("opt");
261 run("fsm");
262 run("opt -fast");
263 run("memory -nomap");
264 run("opt_clean");
265 }
266
267 if (!nobram && check_label("map_bram", "(skip if -nobram)"))
268 {
269 run("memory_bram -rules +/ecp5/bram.txt");
270 run("techmap -map +/ecp5/brams_map.v");
271 }
272
273 if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
274 {
275 run("memory_bram -rules +/ecp5/lutram.txt");
276 run("techmap -map +/ecp5/lutrams_map.v");
277 }
278
279 if (check_label("map_ffram"))
280 {
281 run("opt -fast -mux_undef -undriven -fine");
282 run("memory_map");
283 run("opt -undriven -fine");
284 }
285
286 if (check_label("map_gates"))
287 {
288 if (noccu2)
289 run("techmap");
290 else
291 run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
292 if (retime || help_mode)
293 run("abc -dff", "(only if -retime)");
294 }
295
296 if (check_label("map_ffs"))
297 {
298 run("dffsr2dff");
299 run("dff2dffs");
300 run("opt_clean");
301 if (!nodffe)
302 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
303 run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
304 run("opt_expr -undriven -mux_undef");
305 run("simplemap");
306 run("ecp5_ffinit");
307 run("ecp5_gsr");
308 run("attrmvcp -copy -attr syn_useioff");
309 run("opt_clean");
310 }
311
312 if (check_label("map_luts"))
313 {
314 if (abc2 || help_mode) {
315 run("abc", " (only if -abc2)");
316 }
317 std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
318 if (abc9)
319 techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
320 if (!asyncprld || abc9)
321 run("techmap " + techmap_args);
322
323 if (abc9) {
324 run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
325 run("wbflip @abc9_boxes");
326 run("techmap -autoproc @abc9_boxes");
327 run("aigmap @abc9_boxes");
328 run("wbflip @abc9_boxes");
329 run("read_verilog -icells -lib +/ecp5/abc9_model.v");
330 if (nowidelut)
331 run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
332 else
333 run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
334 run("techmap -map +/ecp5/abc9_unmap.v");
335 } else {
336 if (nowidelut)
337 run("abc -lut 4 -dress");
338 else
339 run("abc -lut 4:7 -dress");
340 }
341 run("clean");
342 }
343
344 if (check_label("map_cells"))
345 {
346 if (vpr)
347 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
348 else
349 run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
350
351 run("clean");
352 }
353
354 if (check_label("check"))
355 {
356 run("autoname");
357 run("hierarchy -check");
358 run("stat");
359 run("check -noinit");
360 }
361
362 if (check_label("blif"))
363 {
364 if (!blif_file.empty() || help_mode) {
365 if (vpr || help_mode) {
366 run(stringf("opt_clean -purge"),
367 " (vpr mode)");
368 run(stringf("write_blif -attr -cname -conn -param %s",
369 help_mode ? "<file-name>" : blif_file.c_str()),
370 " (vpr mode)");
371 }
372 if (!vpr)
373 run(stringf("write_blif -gates -attr -param %s",
374 help_mode ? "<file-name>" : blif_file.c_str()),
375 " (non-vpr mode)");
376 }
377 }
378
379 if (check_label("edif"))
380 {
381 if (!edif_file.empty() || help_mode)
382 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
383 }
384
385 if (check_label("json"))
386 {
387 if (!json_file.empty() || help_mode)
388 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
389 }
390 }
391 } SynthEcp5Pass;
392
393 PRIVATE_NAMESPACE_END