2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 David Shah <dave@ds0.me>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
27 PRIVATE_NAMESPACE_BEGIN
29 struct SynthEcp5Pass
: public ScriptPass
31 SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
33 void help() YS_OVERRIDE
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
37 log(" synth_ecp5 [options]\n");
39 log("This command runs synthesis for ECP5 FPGAs.\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
44 log(" -blif <file>\n");
45 log(" write the design to the specified BLIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
48 log(" -edif <file>\n");
49 log(" write the design to the specified EDIF file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
52 log(" -json <file>\n");
53 log(" write the design to the specified JSON file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
62 log(" do not flatten design before synthesis\n");
65 log(" run 'abc' with -dff option\n");
68 log(" do not use CCU2 cells in output netlist\n");
71 log(" do not use flipflops with CE in output netlist\n");
74 log(" do not use block RAM cells in output netlist\n");
77 log(" do not use LUT RAM cells in output netlist\n");
80 log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
83 log(" use async PRLD mode to implement DLATCH and DFFSR (EXPERIMENTAL)\n");
86 log(" run two passes of 'abc' for slightly improved logic density\n");
89 log(" use new ABC9 flow (EXPERIMENTAL)\n");
92 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
93 log(" (this feature is experimental and incomplete)\n");
96 log(" do not map multipliers to MULT18X18D\n");
99 log("The following commands are executed by this synthesis command:\n");
104 string top_opt
, blif_file
, edif_file
, json_file
;
105 bool noccu2
, nodffe
, nobram
, nolutram
, nowidelut
, asyncprld
, flatten
, retime
, abc2
, abc9
, nodsp
, vpr
;
107 void clear_flags() YS_OVERRIDE
109 top_opt
= "-auto-top";
127 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
129 string run_from
, run_to
;
133 for (argidx
= 1; argidx
< args
.size(); argidx
++)
135 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
136 top_opt
= "-top " + args
[++argidx
];
139 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
140 blif_file
= args
[++argidx
];
143 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
144 edif_file
= args
[++argidx
];
147 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
148 json_file
= args
[++argidx
];
151 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
152 size_t pos
= args
[argidx
+1].find(':');
153 if (pos
== std::string::npos
)
155 run_from
= args
[++argidx
].substr(0, pos
);
156 run_to
= args
[argidx
].substr(pos
+1);
159 if (args
[argidx
] == "-flatten") {
163 if (args
[argidx
] == "-noflatten") {
167 if (args
[argidx
] == "-retime") {
171 if (args
[argidx
] == "-noccu2") {
175 if (args
[argidx
] == "-nodffe") {
179 if (args
[argidx
] == "-nobram") {
183 if (args
[argidx
] == "-asyncprld") {
187 if (args
[argidx
] == "-nolutram" || /*deprecated alias*/ args
[argidx
] == "-nodram") {
191 if (args
[argidx
] == "-nowidelut" || /*deprecated alias*/ args
[argidx
] == "-nomux") {
195 if (args
[argidx
] == "-abc2") {
199 if (args
[argidx
] == "-vpr") {
203 if (args
[argidx
] == "-abc9") {
207 if (args
[argidx
] == "-nodsp") {
213 extra_args(args
, argidx
, design
);
215 if (!design
->full_selection())
216 log_cmd_error("This command only operates on fully selected designs!\n");
219 log_cmd_error("-retime option not currently compatible with -abc9!\n");
221 log_header(design
, "Executing SYNTH_ECP5 pass.\n");
224 run_script(design
, run_from
, run_to
);
229 void script() YS_OVERRIDE
231 if (check_label("begin"))
233 run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
234 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
237 if (check_label("coarse"))
240 if (flatten
|| help_mode
)
242 run("tribuf -logic");
252 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
256 run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
257 run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
263 run("memory -nomap");
267 if (!nobram
&& check_label("map_bram", "(skip if -nobram)"))
269 run("memory_bram -rules +/ecp5/bram.txt");
270 run("techmap -map +/ecp5/brams_map.v");
273 if (!nolutram
&& check_label("map_lutram", "(skip if -nolutram)"))
275 run("memory_bram -rules +/ecp5/lutram.txt");
276 run("techmap -map +/ecp5/lutrams_map.v");
279 if (check_label("map_ffram"))
281 run("opt -fast -mux_undef -undriven -fine");
283 run("opt -undriven -fine");
286 if (check_label("map_gates"))
291 run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
292 if (retime
|| help_mode
)
293 run("abc -dff", "(only if -retime)");
296 if (check_label("map_ffs"))
302 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
303 run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode
? "[-D ASYNC_PRLD]" : (asyncprld
? "-D ASYNC_PRLD" : "")));
304 run("opt_expr -undriven -mux_undef");
308 run("attrmvcp -copy -attr syn_useioff");
312 if (check_label("map_luts"))
314 if (abc2
|| help_mode
) {
315 run("abc", " (only if -abc2)");
317 std::string techmap_args
= asyncprld
? "" : "-map +/ecp5/latches_map.v";
319 techmap_args
+= " -map +/ecp5/abc9_map.v -max_iter 1";
320 if (!asyncprld
|| abc9
)
321 run("techmap " + techmap_args
);
324 run("read_verilog -icells -lib +/ecp5/abc9_model.v");
326 run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
328 run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
329 run("techmap -map +/ecp5/abc9_unmap.v");
332 run("abc -lut 4 -dress");
334 run("abc -lut 4:7 -dress");
339 if (check_label("map_cells"))
342 run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
344 run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
349 if (check_label("check"))
352 run("hierarchy -check");
354 run("check -noinit");
357 if (check_label("blif"))
359 if (!blif_file
.empty() || help_mode
) {
360 if (vpr
|| help_mode
) {
361 run(stringf("opt_clean -purge"),
363 run(stringf("write_blif -attr -cname -conn -param %s",
364 help_mode
? "<file-name>" : blif_file
.c_str()),
368 run(stringf("write_blif -gates -attr -param %s",
369 help_mode
? "<file-name>" : blif_file
.c_str()),
374 if (check_label("edif"))
376 if (!edif_file
.empty() || help_mode
)
377 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
380 if (check_label("json"))
382 if (!json_file
.empty() || help_mode
)
383 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
388 PRIVATE_NAMESPACE_END