8c8f6afaa3e91c77cc5c32f14c1c1888a2452682
[yosys.git] / techlibs / efinix / cells_sim.v
1 module EFX_LUT4(
2 output O,
3 input I0,
4 input I1,
5 input I2,
6 input I3
7 );
8 parameter LUTMASK = 16'h0000;
9 endmodule
10
11 module EFX_ADD(
12 output O,
13 output CO,
14 input I0,
15 input I1,
16 input CI
17 );
18 parameter I0_POLARITY = 1;
19 parameter I1_POLARITY = 1;
20 endmodule
21
22 module EFX_FF(
23 output Q,
24 input D,
25 input CE,
26 input CLK,
27 input SR
28 );
29 parameter CLK_POLARITY = 1;
30 parameter CE_POLARITY = 1;
31 parameter SR_POLARITY = 1;
32 parameter SR_SYNC = 0;
33 parameter SR_VALUE = 0;
34 parameter SR_SYNC_PRIORITY = 0;
35 parameter D_POLARITY = 1;
36 endmodule
37
38 module EFX_GBUFCE(
39 input CE,
40 input I,
41 output O
42 );
43 parameter CE_POLARITY = 1'b1;
44 endmodule
45
46 module EFX_RAM_5K(
47 input [WRITE_WIDTH-1:0] WDATA,
48 input [WRITE_ADDR_WIDTH-1:0] WADDR,
49 input WE,
50 input WCLK,
51 input WCLKE,
52 output [READ_WIDTH-1:0] RDATA,
53 input [READ_ADDR_WIDTH-1:0] RADDR,
54 input RE,
55 input RCLK
56 );
57 parameter READ_WIDTH = 20;
58 parameter WRITE_WIDTH = 20;
59 parameter OUTPUT_REG = 1'b0;
60 parameter RCLK_POLARITY = 1'b1;
61 parameter RE_POLARITY = 1'b1;
62 parameter WCLK_POLARITY = 1'b1;
63 parameter WE_POLARITY = 1'b1;
64 parameter WCLKE_POLARITY = 1'b1;
65 parameter WRITE_MODE = "READ_FIRST";
66 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82 parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83 parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84 parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85 parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86
87 localparam READ_ADDR_WIDTH =
88 (READ_WIDTH == 16) ? 8 : // 256x16
89 (READ_WIDTH == 8) ? 9 : // 512x8
90 (READ_WIDTH == 4) ? 10 : // 1024x4
91 (READ_WIDTH == 2) ? 11 : // 2048x2
92 (READ_WIDTH == 1) ? 12 : // 4096x1
93 (READ_WIDTH == 20) ? 8 : // 256x20
94 (READ_WIDTH == 10) ? 9 : // 512x10
95 (READ_WIDTH == 5) ? 10 : -1; // 1024x5
96
97 localparam WRITE_ADDR_WIDTH =
98 (WRITE_WIDTH == 16) ? 8 : // 256x16
99 (WRITE_WIDTH == 8) ? 9 : // 512x8
100 (WRITE_WIDTH == 4) ? 10 : // 1024x4
101 (WRITE_WIDTH == 2) ? 11 : // 2048x2
102 (WRITE_WIDTH == 1) ? 12 : // 4096x1
103 (WRITE_WIDTH == 20) ? 8 : // 256x20
104 (WRITE_WIDTH == 10) ? 9 : // 512x10
105 (WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
106
107 endmodule