techlibs/efinix/cells_sim.v

   1 module EFX_LUT4(
   2    output O,
   3    input I0,
   4    input I1,
   5    input I2,
   6    input I3
   7 );
   8         parameter LUTMASK = 16'h0000;
   9
  10         wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
  11         wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
  12         wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
  13         assign O = I0 ? s1[1] : s1[0];
  14 endmodule
  15
  16 module EFX_ADD(
  17    output O,
  18    output CO,
  19    input I0,
  20    input I1,
  21    input CI
  22 );
  23    parameter I0_POLARITY   = 1;
  24    parameter I1_POLARITY   = 1;
  25
  26    wire i0;
  27    wire i1;
  28
  29    assign i0 = I0_POLARITY ? I0 : ~I0;
  30    assign i1 = I1_POLARITY ? I1 : ~I1;
  31
  32    assign {CO, O} = i0 + i1 + CI;
  33 endmodule
  34
  35 module EFX_FF(
  36    output reg Q,
  37    input D,
  38    input CE,
  39    input CLK,
  40    input SR
  41 );
  42    parameter CLK_POLARITY = 1;
  43    parameter CE_POLARITY = 1;
  44    parameter SR_POLARITY = 1;
  45    parameter SR_SYNC = 0;
  46    parameter SR_VALUE = 0;
  47    parameter SR_SYNC_PRIORITY = 0;
  48    parameter D_POLARITY = 1;
  49
  50    wire clk;
  51    wire ce;
  52    wire sr;
  53    wire d;
  54    wire prio;
  55    wire sync;
  56    wire async;
  57
  58    assign clk = CLK_POLARITY ? CLK : ~CLK;
  59    assign ce = CE_POLARITY ? CE : ~CE;
  60    assign sr = SR_POLARITY ? SR : ~SR;
  61    assign d = D_POLARITY ? D : ~D;
  62
  63         initial Q = 1'b0;
  64
  65    generate
  66         if (SR_SYNC == 1)
  67       begin
  68          if (SR_SYNC_PRIORITY == 1)
  69          begin
  70             always @(posedge clk)
  71                if (sr)
  72                   Q <= SR_VALUE;
  73                else if (ce)
  74                   Q <= d;
  75          end
  76          else
  77          begin
  78             always @(posedge clk)
  79                if (ce)
  80                begin
  81                   if (sr)
  82                      Q <= SR_VALUE;
  83                   else
  84                      Q <= d;
  85                end
  86          end
  87       end
  88       else
  89       begin
  90          always @(posedge clk or posedge sr)
  91             if (sr)
  92                Q <= SR_VALUE;
  93             else if (ce)
  94                Q <= d;
  95
  96       end
  97    endgenerate
  98 endmodule
  99
 100 module EFX_GBUFCE(
 101    input CE,
 102    input I,
 103    output O
 104 );
 105    parameter CE_POLARITY = 1'b1;
 106
 107    wire ce;
 108    assign ce = CE_POLARITY ? CE : ~CE;
 109
 110    assign O = I & ce;
 111
 112 endmodule
 113
 114 module EFX_RAM_5K(
 115    input [WRITE_WIDTH-1:0] WDATA,
 116    input [WRITE_ADDR_WIDTH-1:0] WADDR,
 117    input WE,
 118    input WCLK,
 119    input WCLKE,
 120    output [READ_WIDTH-1:0] RDATA,
 121    input [READ_ADDR_WIDTH-1:0] RADDR,
 122    input RE,
 123    input RCLK
 124 );
 125    parameter READ_WIDTH = 20;
 126    parameter WRITE_WIDTH = 20;
 127    parameter OUTPUT_REG = 1'b0;
 128    parameter RCLK_POLARITY  = 1'b1;
 129    parameter RE_POLARITY    = 1'b1;
 130    parameter WCLK_POLARITY  = 1'b1;
 131    parameter WE_POLARITY    = 1'b1;
 132    parameter WCLKE_POLARITY = 1'b1;
 133    parameter WRITE_MODE = "READ_FIRST";
 134    parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 135    parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 136    parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 137    parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 138    parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 139    parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 140    parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 141    parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 142    parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 143    parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 144    parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 145    parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 146    parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 147    parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 148    parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 149    parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 150    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 151    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 152    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 153    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 154
 155    localparam READ_ADDR_WIDTH =
 156                             (READ_WIDTH == 16) ? 8 :  // 256x16
 157                             (READ_WIDTH == 8)  ? 9 :  // 512x8
 158                             (READ_WIDTH == 4)  ? 10 : // 1024x4
 159                             (READ_WIDTH == 2)  ? 11 : // 2048x2
 160                             (READ_WIDTH == 1)  ? 12 : // 4096x1
 161                             (READ_WIDTH == 20) ? 8 :  // 256x20
 162                             (READ_WIDTH == 10) ? 9 :  // 512x10
 163                             (READ_WIDTH == 5)  ? 10 : -1; // 1024x5
 164
 165    localparam WRITE_ADDR_WIDTH =
 166                             (WRITE_WIDTH == 16) ? 8 :  // 256x16
 167                             (WRITE_WIDTH == 8)  ? 9 :  // 512x8
 168                             (WRITE_WIDTH == 4)  ? 10 : // 1024x4
 169                             (WRITE_WIDTH == 2)  ? 11 : // 2048x2
 170                             (WRITE_WIDTH == 1)  ? 12 : // 4096x1
 171                             (WRITE_WIDTH == 20) ? 8 :  // 256x20
 172                             (WRITE_WIDTH == 10) ? 9 :  // 512x10
 173                             (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
 174
 175 endmodule