techlibs/efinix/cells_sim.v

   1 module EFX_LUT4(
   2    output O,
   3    input I0,
   4    input I1,
   5    input I2,
   6    input I3
   7 );
   8         parameter LUTMASK = 16'h0000;
   9
  10         wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
  11         wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
  12         wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
  13         assign O = I0 ? s1[1] : s1[0];
  14 endmodule
  15
  16 module EFX_ADD(
  17    output O,
  18    output CO,
  19    input I0,
  20    input I1,
  21    input CI
  22 );
  23    parameter I0_POLARITY   = 1;
  24    parameter I1_POLARITY   = 1;
  25
  26    wire i0;
  27    wire i1;
  28
  29    assign i0 = I0_POLARITY ? I0 : ~I0;
  30    assign i1 = I1_POLARITY ? I1 : ~I1;
  31
  32    assign {CO, O} = i0 + i1 + CI;
  33 endmodule
  34
  35 module EFX_FF(
  36    output reg Q,
  37    input D,
  38    input CE,
  39    input CLK,
  40    input SR
  41 );
  42    parameter CLK_POLARITY = 1;
  43    parameter CE_POLARITY = 1;
  44    parameter SR_POLARITY = 1;
  45    parameter SR_SYNC = 0;
  46    parameter SR_VALUE = 0;
  47    parameter SR_SYNC_PRIORITY = 0;
  48    parameter D_POLARITY = 1;
  49
  50    wire clk;
  51    wire ce;
  52    wire sr;
  53    wire d;
  54    wire prio;
  55    wire sync;
  56    wire async;
  57
  58    assign clk = CLK_POLARITY ? CLK : ~CLK;
  59    assign ce = CE_POLARITY ? CE : ~CE;
  60    assign sr = SR_POLARITY ? SR : ~SR;
  61    assign d = D_POLARITY ? D : ~D;
  62
  63    generate
  64         if (SR_SYNC == 1)
  65       begin
  66          if (SR_SYNC_PRIORITY == 1)
  67          begin
  68             always @(posedge clk)
  69                if (sr)
  70                   Q <= SR_VALUE;
  71                else if (ce)
  72                   Q <= d;
  73          end
  74          else
  75          begin
  76             always @(posedge clk)
  77                if (ce)
  78                begin
  79                   if (sr)
  80                      Q <= SR_VALUE;
  81                   else
  82                      Q <= d;
  83                end
  84          end
  85       end
  86       else
  87       begin
  88          always @(posedge clk or posedge sr)
  89             if (sr)
  90                Q <= SR_VALUE;
  91             else if (ce)
  92                Q <= d;
  93
  94       end
  95    endgenerate
  96 endmodule
  97
  98 module EFX_GBUFCE(
  99    input CE,
 100    input I,
 101    output O
 102 );
 103    parameter CE_POLARITY = 1'b1;
 104
 105    wire ce;
 106    assign ce = CE_POLARITY ? CE : ~CE;
 107
 108    assign O = I & ce;
 109
 110 endmodule
 111
 112 module EFX_RAM_5K(
 113    input [WRITE_WIDTH-1:0] WDATA,
 114    input [WRITE_ADDR_WIDTH-1:0] WADDR,
 115    input WE,
 116    input WCLK,
 117    input WCLKE,
 118    output [READ_WIDTH-1:0] RDATA,
 119    input [READ_ADDR_WIDTH-1:0] RADDR,
 120    input RE,
 121    input RCLK
 122 );
 123    parameter READ_WIDTH = 20;
 124    parameter WRITE_WIDTH = 20;
 125    parameter OUTPUT_REG = 1'b0;
 126    parameter RCLK_POLARITY  = 1'b1;
 127    parameter RE_POLARITY    = 1'b1;
 128    parameter WCLK_POLARITY  = 1'b1;
 129    parameter WE_POLARITY    = 1'b1;
 130    parameter WCLKE_POLARITY = 1'b1;
 131    parameter WRITE_MODE = "READ_FIRST";
 132    parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 133    parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 134    parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 135    parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 136    parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 137    parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 138    parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 139    parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 140    parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 141    parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 142    parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 143    parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 144    parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 145    parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 146    parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 147    parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 148    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 149    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 150    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 151    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 152
 153    localparam READ_ADDR_WIDTH =
 154                             (READ_WIDTH == 16) ? 8 :  // 256x16
 155                             (READ_WIDTH == 8)  ? 9 :  // 512x8
 156                             (READ_WIDTH == 4)  ? 10 : // 1024x4
 157                             (READ_WIDTH == 2)  ? 11 : // 2048x2
 158                             (READ_WIDTH == 1)  ? 12 : // 4096x1
 159                             (READ_WIDTH == 20) ? 8 :  // 256x20
 160                             (READ_WIDTH == 10) ? 9 :  // 512x10
 161                             (READ_WIDTH == 5)  ? 10 : -1; // 1024x5
 162
 163    localparam WRITE_ADDR_WIDTH =
 164                             (WRITE_WIDTH == 16) ? 8 :  // 256x16
 165                             (WRITE_WIDTH == 8)  ? 9 :  // 512x8
 166                             (WRITE_WIDTH == 4)  ? 10 : // 1024x4
 167                             (WRITE_WIDTH == 2)  ? 11 : // 2048x2
 168                             (WRITE_WIDTH == 1)  ? 12 : // 4096x1
 169                             (WRITE_WIDTH == 20) ? 8 :  // 256x20
 170                             (WRITE_WIDTH == 10) ? 9 :  // 512x10
 171                             (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
 172
 173 endmodule