techlibs/efinix/efinix_gbuf.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
   5  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include "kernel/yosys.h"
  22 #include "kernel/sigtools.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 static void handle_gbufs(Module *module)
  28 {
  29         SigMap sigmap(module);
  30
  31         pool<SigBit> clk_bits;
  32         dict<SigBit, SigBit> rewrite_bits;
  33         vector<pair<Cell*, SigBit>> pad_bits;
  34
  35         for (auto cell : module->cells())
  36         {
  37                 if (cell->type == "\\EFX_FF") {
  38                         for (auto bit : sigmap(cell->getPort("\\CLK")))
  39                                 clk_bits.insert(bit);
  40                 }
  41                 if (cell->type == "\\EFX_RAM_5K") {
  42                         for (auto bit : sigmap(cell->getPort("\\RCLK")))
  43                                 clk_bits.insert(bit);
  44                         for (auto bit : sigmap(cell->getPort("\\WCLK")))
  45                                 clk_bits.insert(bit);
  46                 }
  47         }
  48
  49         for (auto wire : vector<Wire*>(module->wires()))
  50         {
  51                 if (!wire->port_input)
  52                         continue;
  53
  54                 for (int index = 0; index < GetSize(wire); index++)
  55                 {
  56                         SigBit bit(wire, index);
  57                         SigBit canonical_bit = sigmap(bit);
  58
  59                         if (!clk_bits.count(canonical_bit))
  60                                 continue;
  61
  62                         Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
  63                         SigBit new_bit = module->addWire(NEW_ID);
  64                         c->setParam("\\CE_POLARITY", State::S1);
  65                         c->setPort("\\O", new_bit);
  66                         c->setPort("\\CE", State::S1);
  67                         pad_bits.push_back(make_pair(c, bit));
  68                         rewrite_bits[canonical_bit] = new_bit;
  69
  70                         log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
  71                 }
  72         }
  73
  74         auto rewrite_function = [&](SigSpec &s) {
  75                 for (auto &bit : s) {
  76                         SigBit canonical_bit = sigmap(bit);
  77                         if (rewrite_bits.count(canonical_bit))
  78                                 bit = rewrite_bits.at(canonical_bit);
  79                 }
  80         };
  81
  82         module->rewrite_sigspecs(rewrite_function);
  83
  84         for (auto &it : pad_bits)
  85                 it.first->setPort("\\I", it.second);
  86 }
  87
  88 struct EfinixGbufPass : public Pass {
  89         EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
  90         void help() YS_OVERRIDE
  91         {
  92                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  93                 log("\n");
  94                 log("    efinix_gbuf [options] [selection]\n");
  95                 log("\n");
  96                 log("Add Efinix global clock buffers to top module as needed.\n");
  97                 log("\n");
  98         }
  99         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 100         {
 101                 log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
 102
 103                 size_t argidx;
 104                 for (argidx = 1; argidx < args.size(); argidx++)
 105                 {
 106                         break;
 107                 }
 108                 extra_args(args, argidx, design);
 109
 110                 Module *module = design->top_module();
 111
 112                 if (module == nullptr)
 113                         log_cmd_error("No top module found.\n");
 114
 115                 handle_gbufs(module);
 116         }
 117 } EfinixGbufPass;
 118
 119 PRIVATE_NAMESPACE_END