2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2019 Miodrag Milanovic <micko@yosyshq.com>
5 * Copyright (C) 2019 Claire Xenia Wolf <claire@yosyshq.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
27 PRIVATE_NAMESPACE_BEGIN
29 struct SynthEfinixPass
: public ScriptPass
31 SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { }
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
37 log(" synth_efinix [options]\n");
39 log("This command runs synthesis for Efinix FPGAs.\n");
41 log(" -top <module>\n");
42 log(" use the specified module as top module\n");
44 log(" -edif <file>\n");
45 log(" write the design to the specified EDIF file. writing of an output file\n");
46 log(" is omitted if this parameter is not specified.\n");
48 log(" -json <file>\n");
49 log(" write the design to the specified JSON file. writing of an output file\n");
50 log(" is omitted if this parameter is not specified.\n");
52 log(" -run <from_label>:<to_label>\n");
53 log(" only run the commands between the labels (see below). an empty\n");
54 log(" from label is synonymous to 'begin', and empty to label is\n");
55 log(" synonymous to the end of the command list.\n");
58 log(" do not flatten design before synthesis\n");
61 log(" run 'abc' with '-dff -D 1' options\n");
64 log(" do not use EFX_RAM_5K cells in output netlist\n");
67 log("The following commands are executed by this synthesis command:\n");
72 string top_opt
, edif_file
, json_file
;
73 bool flatten
, retime
, nobram
;
75 void clear_flags() override
77 top_opt
= "-auto-top";
85 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
87 string run_from
, run_to
;
91 for (argidx
= 1; argidx
< args
.size(); argidx
++)
93 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
94 top_opt
= "-top " + args
[++argidx
];
97 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
98 edif_file
= args
[++argidx
];
101 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
102 json_file
= args
[++argidx
];
105 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
106 size_t pos
= args
[argidx
+1].find(':');
107 if (pos
== std::string::npos
)
109 run_from
= args
[++argidx
].substr(0, pos
);
110 run_to
= args
[argidx
].substr(pos
+1);
113 if (args
[argidx
] == "-noflatten") {
117 if (args
[argidx
] == "-retime") {
121 if (args
[argidx
] == "-nobram") {
127 extra_args(args
, argidx
, design
);
129 if (!design
->full_selection())
130 log_cmd_error("This command only operates on fully selected designs!\n");
132 log_header(design
, "Executing SYNTH_EFINIX pass.\n");
135 run_script(design
, run_from
, run_to
);
140 void script() override
142 if (check_label("begin"))
144 run("read_verilog -lib +/efinix/cells_sim.v");
145 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
148 if (flatten
&& check_label("flatten", "(unless -noflatten)"))
152 run("tribuf -logic");
156 if (check_label("coarse"))
158 run("synth -run coarse");
161 if (!nobram
|| check_label("map_bram", "(skip if -nobram)"))
163 run("memory_bram -rules +/efinix/brams.txt");
164 run("techmap -map +/efinix/brams_map.v");
165 run("setundef -zero -params t:EFX_RAM_5K");
168 if (check_label("map_ffram"))
170 run("opt -fast -mux_undef -undriven -fine");
172 run("opt -undriven -fine");
175 if (check_label("map_gates"))
177 run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
179 if (retime
|| help_mode
)
180 run("abc -dff -D 1", "(only if -retime)");
183 if (check_label("map_ffs"))
185 run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
186 run("techmap -D NO_LUT -map +/efinix/cells_map.v");
187 run("opt_expr -mux_undef");
191 if (check_label("map_luts"))
197 if (check_label("map_cells"))
199 run("techmap -map +/efinix/cells_map.v");
203 if (check_label("map_gbuf"))
205 run("clkbufmap -buf $__EFX_GBUF O:I");
206 run("techmap -map +/efinix/gbuf_map.v");
207 run("efinix_fixcarry");
211 if (check_label("check"))
213 run("hierarchy -check");
215 run("check -noinit");
216 run("blackbox =A:whitebox");
219 if (check_label("edif"))
221 if (!edif_file
.empty() || help_mode
)
222 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
225 if (check_label("json"))
227 if (!json_file
.empty() || help_mode
)
228 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
233 PRIVATE_NAMESPACE_END