techlibs/gowin/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
   5  *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 (* techmap_celltype = "$alu" *)
  22 module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
  23    parameter A_SIGNED = 0;
  24    parameter B_SIGNED = 0;
  25    parameter A_WIDTH = 1;
  26    parameter B_WIDTH = 1;
  27    parameter Y_WIDTH = 1;
  28
  29    (* force_downto *)
  30    input [A_WIDTH-1:0] A;
  31    (* force_downto *)
  32    input [B_WIDTH-1:0] B;
  33    (* force_downto *)
  34    output [Y_WIDTH-1:0] X, Y;
  35
  36    input                CI, BI;
  37    (* force_downto *)
  38    output [Y_WIDTH-1:0] CO;
  39
  40    wire                 _TECHMAP_FAIL_ = Y_WIDTH <= 2;
  41
  42    (* force_downto *)
  43    wire [Y_WIDTH-1:0]   A_buf, B_buf;
  44    \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
  45    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
  46
  47    (* force_downto *)
  48    wire [Y_WIDTH-1:0]   AA = A_buf;
  49    (* force_downto *)
  50    wire [Y_WIDTH-1:0]   BB = B_buf;
  51    (* force_downto *)
  52    wire [Y_WIDTH-1:0]   C = {CO, CI};
  53
  54    genvar               i;
  55    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
  56       ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub
  57       alu(.I0(AA[i]),
  58           .I1(BB[i]),
  59           .I3(~BI),
  60           .CIN(C[i]),
  61           .COUT(CO[i]),
  62           .SUM(Y[i])
  63           );
  64    end endgenerate
  65    assign X = AA ^ BB;
  66 endmodule
  67