Merge remote-tracking branch 'upstream/master'
[yosys.git] / techlibs / gowin / arith_map.v
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 David Shah <dave@ds0.me>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 (* techmap_celltype = "$alu" *)
22 module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
23 parameter A_SIGNED = 0;
24 parameter B_SIGNED = 0;
25 parameter A_WIDTH = 1;
26 parameter B_WIDTH = 1;
27 parameter Y_WIDTH = 1;
28
29 input [A_WIDTH-1:0] A;
30 input [B_WIDTH-1:0] B;
31 output [Y_WIDTH-1:0] X, Y;
32
33 input CI, BI;
34 output [Y_WIDTH-1:0] CO;
35
36 wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
37
38 wire [Y_WIDTH-1:0] A_buf, B_buf;
39 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
40 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
41
42 wire [Y_WIDTH-1:0] AA = A_buf;
43 wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
44 wire [Y_WIDTH-1:0] C = {CO, CI};
45
46 genvar i;
47 generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
48 ALU #(.ALU_MODE(32'b0))
49 alu(.I0(AA[i]),
50 .I1(BB[i]),
51 .I3(1'b0),
52 .CIN(C[i]),
53 .COUT(CO[i]),
54 .SUM(Y[i])
55 );
56 end endgenerate
57 assign X = AA ^ BB;
58 endmodule
59