techlibs/gowin/brams_map.v

   1 /* Semi Dual Port (SDP) memory have the following configurations:
   2  * Memory Config    RAM(BIT)   Port Mode   Memory Depth   Data Depth
   3  * ----------------|---------| ----------|--------------|------------|
   4  * B-SRAM_16K_SD1      16K      16Kx1       16,384           1
   5  * B-SRAM_8K_SD2       16K       8Kx2        8,192           2
   6  * B-SRAM_4K_SD4       16K       4Kx2        4,096           4
   7  */
   8 module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   9         parameter CFG_ABITS = 10;
  10         parameter CFG_DBITS = 16;
  11         parameter CFG_ENABLE_A = 1;
  12         parameter [16383:0] INIT = 16384'hx;
  13         parameter CLKPOL2 = 1;
  14         parameter CLKPOL3 = 1;
  15
  16         input CLK2;
  17         input CLK3;
  18
  19         input [CFG_ABITS-1:0] A1ADDR;
  20         input [CFG_DBITS-1:0] A1DATA;
  21         input [CFG_ENABLE_A-1:0] A1EN;
  22
  23         input [CFG_ABITS-1:0] B1ADDR;
  24         output [CFG_DBITS-1:0] B1DATA;
  25         input B1EN;
  26
  27         wire [31-CFG_DBITS:0] open;
  28
  29
  30         generate if (CFG_DBITS == 1) begin
  31                 SDP   #(
  32       `include "bram_init_16.vh"
  33                         .READ_MODE(0),
  34                         .BIT_WIDTH_0(1),
  35                         .BIT_WIDTH_1(1),
  36                         .BLK_SEL(3'b000),
  37                         .RESET_MODE("SYNC")
  38                 ) _TECHMAP_REPLACE_ (
  39                         .CLKA(CLK2),   .CLKB(CLK3),
  40                         .WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
  41                         .WREB(1'b0),   .CEB(B1EN),
  42                         .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
  43                         .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
  44                         .DO({open, B1DATA}),
  45                         .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
  46                         .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
  47                 );
  48         end else if (CFG_DBITS == 2) begin
  49                 SDP    #(
  50       `include "bram_init_16.vh"
  51                         .READ_MODE(0),
  52                         .BIT_WIDTH_0(2),
  53                         .BIT_WIDTH_1(2),
  54                         .BLK_SEL(3'b000),
  55                         .RESET_MODE("SYNC")
  56                 ) _TECHMAP_REPLACE_ (
  57                         .CLKA(CLK2),   .CLKB(CLK3),
  58                         .WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
  59                         .WREB(1'b0),   .CEB(B1EN),
  60                         .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
  61                         .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
  62                         .DO({open, B1DATA}),
  63                         .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
  64                         .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
  65                 );
  66         end else if (CFG_DBITS <= 4) begin
  67                 SDP    #(
  68       `include "bram_init_16.vh"
  69                         .READ_MODE(0),
  70                         .BIT_WIDTH_0(4),
  71                         .BIT_WIDTH_1(4),
  72                         .BLK_SEL(3'b000),
  73                         .RESET_MODE("SYNC")
  74                 ) _TECHMAP_REPLACE_ (
  75                         .CLKA(CLK2),   .CLKB(CLK3),
  76                         .WREA(A1EN),   .OCE(1'b0),
  77                         .WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
  78                         .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
  79                         .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
  80                         .DO({open, B1DATA}),
  81                         .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
  82                         .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
  83                 );
  84         end else if (CFG_DBITS <= 8) begin
  85                 SDP    #(
  86       `include "bram_init_16.vh"
  87                         .READ_MODE(0),
  88                         .BIT_WIDTH_0(8),
  89                         .BIT_WIDTH_1(8),
  90                         .BLK_SEL(3'b000),
  91                         .RESET_MODE("SYNC")
  92                 ) _TECHMAP_REPLACE_ (
  93                         .CLKA(CLK2),   .CLKB(CLK3),
  94                         .WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
  95                         .WREB(1'b0),   .CEB(B1EN),
  96                         .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
  97                         .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
  98                         .DO({open, B1DATA}),
  99                         .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
 100                         .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 101                 );
 102         end else if (CFG_DBITS <= 16) begin
 103                 SDP    #(
 104       `include "bram_init_16.vh"
 105                         .READ_MODE(0),
 106                         .BIT_WIDTH_0(16),
 107                         .BIT_WIDTH_1(16),
 108                         .BLK_SEL(3'b000),
 109                         .RESET_MODE("SYNC")
 110                 ) _TECHMAP_REPLACE_ (
 111                         .CLKA(CLK2),   .CLKB(CLK3),
 112                         .WREA(|A1EN),   .OCE(1'b0),
 113                         .WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
 114                         .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
 115                         .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
 116                         .DO({open, B1DATA}),
 117                         .ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, A1EN}),
 118                         .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 119                 );
 120         end else if (CFG_DBITS <= 32) begin
 121                 SDP    #(
 122       `include "bram_init_16.vh"
 123                         .READ_MODE(0),
 124                         .BIT_WIDTH_0(32),
 125                         .BIT_WIDTH_1(32),
 126                         .BLK_SEL(3'b000),
 127                         .RESET_MODE("SYNC")
 128                 ) _TECHMAP_REPLACE_ (
 129                         .CLKA(CLK2),   .CLKB(CLK3),
 130                         .WREA(|A1EN),   .OCE(1'b0),
 131                         .WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
 132                         .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
 133                         .DI(A1DATA),
 134                         .DO(B1DATA),
 135                         .ADA({A1ADDR, {(10-CFG_ABITS){1'b0}}, A1EN}),
 136                         .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
 137                 );
 138         end else begin
 139                 wire TECHMAP_FAIL = 1'b1;
 140         end endgenerate
 141
 142 endmodule