Merge branch 'eddie/abc9_refactor' into xaig_dff
[yosys.git] / techlibs / gowin / cells_map.v
1 module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
2 module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
3
4 module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
5 module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
6 module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
7
8 module \$lut (A, Y);
9 parameter WIDTH = 0;
10 parameter LUT = 0;
11
12 input [WIDTH-1:0] A;
13 output Y;
14
15 generate
16 if (WIDTH == 1) begin
17 LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
18 .I0(A[0]));
19 end else
20 if (WIDTH == 2) begin
21 LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
22 .I0(A[0]), .I1(A[1]));
23 end else
24 if (WIDTH == 3) begin
25 LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
26 .I0(A[0]), .I1(A[1]), .I2(A[2]));
27 end else
28 if (WIDTH == 4) begin
29 LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
30 .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
31 end else begin
32 wire _TECHMAP_FAIL_ = 1;
33 end
34 endgenerate
35 endmodule