techlibs/gowin/cells_map.v

   1 `default_nettype none
   2 //All DFF* have INIT, but the hardware is always initialised to the reset
   3 //value regardless. The parameter is ignored.
   4
   5 // DFFN                  D Flip-Flop with Negative-Edge Clock
   6 module  \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
   7         generate
   8                 if (_TECHMAP_WIREINIT_Q_ === 1'b1)
   9                         DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
  10                 else
  11                         DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
  12         endgenerate
  13         wire _TECHMAP_REMOVEINIT_Q_ = 1;
  14 endmodule
  15
  16 // DFF                   D Flip-Flop
  17 module  \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
  18         generate
  19                 if (_TECHMAP_WIREINIT_Q_ === 1'b1)
  20                         DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
  21                 else
  22                         DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
  23         endgenerate
  24         wire _TECHMAP_REMOVEINIT_Q_ = 1;
  25 endmodule
  26
  27 // DFFE                  D Flip-Flop with Clock Enable
  28 module  \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
  29         generate
  30                 if (_TECHMAP_WIREINIT_Q_ === 1'b1)
  31                         DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
  32                 else
  33                         DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
  34         endgenerate
  35         wire _TECHMAP_REMOVEINIT_Q_ = 1;
  36 endmodule
  37
  38 module  \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
  39         generate
  40                 if (_TECHMAP_WIREINIT_Q_ === 1'b1)
  41                         DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
  42                 else
  43                         DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
  44         endgenerate
  45         wire _TECHMAP_REMOVEINIT_Q_ = 1;
  46 endmodule
  47
  48 // DFFNE                 D Flip-Flop with Negative-Edge Clock and Clock Enable
  49 module  \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
  50         generate
  51                 if (_TECHMAP_WIREINIT_Q_ === 1'b1)
  52                         DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
  53                 else
  54                         DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
  55         endgenerate
  56         wire _TECHMAP_REMOVEINIT_Q_ = 1;
  57 endmodule
  58
  59 module  \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
  60         generate
  61                 if (_TECHMAP_WIREINIT_Q_ === 1'b1)
  62                         DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
  63                 else
  64                         DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
  65         endgenerate
  66         wire _TECHMAP_REMOVEINIT_Q_ = 1;
  67 endmodule
  68
  69 // DFFR                  D Flip-Flop with Synchronous Reset
  70 module  \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
  71         DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
  72         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
  73 endmodule
  74
  75 module  \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
  76         DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
  77         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
  78 endmodule
  79
  80 // DFFNR                 D Flip-Flop with Negative-Edge Clock and Synchronous Reset
  81 module  \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
  82         DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
  83         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
  84 endmodule
  85 module  \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
  86         DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
  87         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
  88 endmodule
  89
  90 // DFFRE                 D Flip-Flop with Clock Enable and Synchronous Reset
  91 module  \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
  92         DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
  93         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
  94 endmodule
  95 module  \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
  96         DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
  97         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
  98 endmodule
  99
 100 // DFFNRE                D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
 101 module  \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 102         DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
 103         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 104 endmodule
 105 module  \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 106         DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
 107         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 108 endmodule
 109
 110 // DFFS                  D Flip-Flop with Synchronous Set
 111 module  \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 112         DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
 113         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 114 endmodule
 115 module  \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 116         DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
 117         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 118 endmodule
 119
 120 // DFFNS                 D Flip-Flop with Negative-Edge Clock and Synchronous Set
 121 module  \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 122         DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
 123         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 124 endmodule
 125 module  \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 126         DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
 127         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 128 endmodule
 129
 130 // DFFSE                 D Flip-Flop with Clock Enable and Synchronous Set
 131 module  \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 132         DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
 133         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 134 endmodule
 135 module  \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 136         DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
 137         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 138 endmodule
 139
 140 // DFFNSE                D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
 141 module  \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 142         DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
 143         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 144 endmodule
 145 module  \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 146         DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
 147         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 148 endmodule
 149
 150 // DFFP                  D Flip-Flop with Asynchronous Preset
 151 module  \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 152         DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
 153         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 154 endmodule
 155 module  \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 156         DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
 157         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 158 endmodule
 159
 160 // DFFNP                 D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
 161 module  \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 162         DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
 163         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 164 endmodule
 165 module  \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 166         DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
 167         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 168 endmodule
 169
 170 // DFFC                  D Flip-Flop with Asynchronous Clear
 171 module  \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 172         DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
 173         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 174 endmodule
 175 module  \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 176         DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
 177         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 178 endmodule
 179
 180 // DFFNC                 D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
 181 module  \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 182         DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
 183         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 184 endmodule
 185 module  \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
 186         DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
 187         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 188 endmodule
 189
 190 // DFFPE                 D Flip-Flop with Clock Enable and Asynchronous Preset
 191 module  \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 192         DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
 193         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 194 endmodule
 195 module  \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 196         DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
 197         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 198 endmodule
 199
 200 // DFFNPE                D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
 201 module  \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 202         DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
 203         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 204 endmodule
 205 module  \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 206         DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
 207         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
 208 endmodule
 209
 210 // DFFCE                 D Flip-Flop with Clock Enable and Asynchronous Clear
 211 module  \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 212         DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
 213         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 214 endmodule
 215 module  \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 216         DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
 217         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 218 endmodule
 219
 220 // DFFNCE                D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
 221 module  \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 222         DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
 223         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 224 endmodule
 225 module  \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
 226         DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
 227         wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
 228 endmodule
 229
 230
 231 module \$lut (A, Y);
 232         parameter WIDTH = 0;
 233         parameter LUT = 0;
 234
 235         (* force_downto *)
 236         input [WIDTH-1:0] A;
 237         output Y;
 238
 239         generate
 240                 if (WIDTH == 1) begin
 241                         LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
 242                                 .I0(A[0]));
 243                 end else
 244                 if (WIDTH == 2) begin
 245                         LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
 246                                 .I0(A[0]), .I1(A[1]));
 247                 end else
 248                 if (WIDTH == 3) begin
 249                         LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
 250                                 .I0(A[0]), .I1(A[1]), .I2(A[2]));
 251                 end else
 252                 if (WIDTH == 4) begin
 253                         LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
 254                                 .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
 255                 end else
 256                 if (WIDTH == 5) begin
 257                         wire f0, f1;
 258                         \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
 259                         \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
 260                         MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
 261                 end else
 262                 if (WIDTH == 6) begin
 263                         wire f0, f1;
 264                         \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
 265                         \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
 266                         MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
 267                 end else
 268                 if (WIDTH == 7) begin
 269                         wire f0, f1;
 270                         \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
 271                         \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
 272                         MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
 273                 end else
 274                 if (WIDTH == 8) begin
 275                         wire f0, f1;
 276                         \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
 277                         \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
 278                         MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
 279                 end else begin
 280                         wire _TECHMAP_FAIL_ = 1;
 281                 end
 282         endgenerate
 283 endmodule